バウンダリ・スキャンおよびJTAG
最先端のバウンダリ・スキャン・テクノロジー
本サイトは、Agilentのテクノロジーとソリューションをより良く理解していただくためのサイトです。
Agilentは、最近7つの国際的な賞を受賞したこともあり、バウンダリ・スキャン・テクノロジーがテストの目的に必要となった今、20年間先駆者でありつづけたことが再確認されています。Agilentは、Agilentのバウンダリ・スキャン・ソリューションのベースであるIEEE 1149.1規格の発表以来、お客様およびお客様の顧客からのご要望に応え、このテクノロジーに投資してきました。
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Testing DDR Memory; How On-Chip DFT Helps
This paper discusses DDR memory testing challenges we see today, and how the adoption of DFT capabilities pays off in higher test coverage, better diagnostics and reduced programming/support time.
記事 2012-04-17 |
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530 KB
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Boundary-Scan Advanced Diagnostic Methods
This paper illustrates how usage of boundary scan circuit information and predictive analysis of potential assembly faults will provide more precise and accurate diagnostic information.
記事 2012-04-17 |
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1.20 MB
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Silicon Nails increases your test coverage
デモ 2011-07-22 |
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How to build a fixture for use with the Agilent Cover-Extend Technology
Cover-Extend Technology is Agilent’s latest limited access solution for in-circuit test. This paper documents the necessary information for a fixture vendor to build a Cover-Extend fixture.
アプリケーション・ノート 2011-06-24 |
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1.09 MB
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Solutions for Undetected Shorts on IEEE 1149.1 Self-Monitoring Pins
This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins, and potential mitigating solutions.
記事 2010-12-10 |
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789 KB
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Surviving State Disruptions Caused by Test: the "Lobotomy Problem"
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE
記事 2010-12-10 |
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402 KB
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Principal Component Analysis-Based Compensation for Measurement Errors
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE
記事 2010-12-10 |
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1.10 MB
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Limited Access Tools Improve Test Coverage
Smaller test pads and shrinking board sizes are posing new challenges, and driving innovations to overcome limited access with new test solutions. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend
記事 2010-10-20 |
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275 KB
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The Proposed IEEE Test Standards
There is a resurgence of interest in Boundary Scan and Built in Self Test (BIST) initiatives to be part of IEEE standards. This article explains the IEEE standard and their benefits to the industry. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend
記事 2010-10-20 |
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2.83 MB
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Boundary Scan Press Releases
プレス資料 2010-07-14 |
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Comparing Boundary Scan Methods White Paper
The need for reusable tests is driving standalone boundary scan-ICT integration. This article first appeared in the September 2009 issue of Circuits Assembly and is reprinted with kind permission.
記事 2010-06-09 |
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2.68 MB
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Medalist VTEP v2.0 Powered, with Cover-Extend technology
This brochure provides an overview of Cover-Extend under the VTEP v2.0 Powered vectorless test suite
ブローシャ 2010-04-06 |
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237 KB
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Medalist i3070 In Circuit Test – Utilizing the most comprehensive Limited Access
This article introduces the seven most prominent and effective limited access tools on the Agilent Medalist i3070 ICT, collectively known Super 7 suite.
アプリケーション・ノート 2009-03-06 |
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342 KB
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