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Digital Design & Interconnect Standards

Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.

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B4621B for DDR2, DDR3, or DDR4 Debug and Validation - Data Sheet 
The B4621B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for double- edge data-rate captures up to 2.5Gb/s.

Data Sheet 2012-09-04

PDF PDF 1.32 MB
B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet 
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.

Data Sheet 2012-09-03

PDF PDF 1.03 MB
J-BERT N4903B High-Performance Serial BERT - Data Sheet Version 1.3 
This data sheet documents the capabilities of the N4906B, Agilent's high-performance serial BERT for R&D characterization compliance testing and for manufacturing volume ramp testing.

Data Sheet 2013-04-10

PDF PDF 1.90 MB
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U4301A PCI Express® 3.0 Analyzer Module - Data Sheet 
Agilent's U4301A PCI Express® 3.0 analyzer module is a protocol analyzer supporting all PCIe applications from Gen1 - Gen3 and speeds from 2.5 GT/s (Gen1) - PCI 8 GT/s (Gen3), link widths X1-X16.

Data Sheet 2013-05-08

PDF PDF 4.92 MB
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