デジタル・デザインとインターコネクト規格
Agilentによる最高のデザインの支援。高速規格に対応し、お客様の高速デジタル・デザイン・サイクル（デザイン／シミュレーション／解析／デバッグ／コンプライアンス／シグナル・インテグリティ）に適合する、最適なソリューションをご検討いただけます。
絞込みのリセット1-23 / 23
|
組み込み開発エンジニア向けデバッグ・セミナ ～DDR, USB2.0, FPGAのデバッグの勘所～
2012年度 開催のご案内
セミナのプレゼンテーション 2012-02-16 |
PDF
262 KB
|
|
高速デジタル設計を成功に導く、ADS、EMPro、SystemVue ワークショップ資料
このセルフガイド・ワークショップの資料は、ADS 2011の最新の高速デジタル機能を紹介しています。
セミナのプレゼンテーション 2011-09-29 |
|
|
ADMF: Facing the challenges of Super speed USB 3.0 Product Development
Agilent Digital Measurement Forum (ADMF): Facing the challenges of Super speed USB Product Development
セミナのプレゼンテーション 2008-11-12 |
PDF
1.78 MB
|
|
Analyzing Digital Jitter and its Component eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
35 KB
|
|
Building a Precision Jitter Source
Presentation, June 1, 2004
From the Japan Agilent Digital Measurement Forum, this presentation reviews the construction of a precision jitter source for analyzing digital jitter measurements.
セミナのプレゼンテーション 2004-06-01 |
PDF
623 KB
|
|
Characterization and Modeling of a High Speed Backplane Differential Channels eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
80 KB
|
|
Hacking the Backplane:Complete Differential Channel Characterization & Analysis from 4-port Meas.
セミナのプレゼンテーション 2008-11-09 |
|
|
Introduction to EMI/EMC Challenges and Their Solution
Agilent EEsof EDA presentation on how to, "Overcome High Speed Digital Design Challenges".
セミナのプレゼンテーション 2012-02-16 |
PDF
3.46 MB
|
|
Jitter Analysis: What Works, What Doesn't & Why eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
63 KB
|
|
Jitter in Digital Circuits eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
34 KB
|
|
Jitter Measurements for High-Speed Digital
Jitter Measurements for High-Speed Digital
Transmission
セミナのプレゼンテーション 2006-06-14 |
PDF
44 KB
|
|
Jitter Measurements with a High-Speed Scope eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
117 KB
|
|
Minimizing Crosstalk in Hi-Speed Interconnects using Measurement-based Modeling
This Presentation presented by Mike Resso (Agilent Technologies) focuses on minimizing crosstalk in high speed interconnects using measurement-based modeling.
セミナのプレゼンテーション 2006-09-01 |
PDF
1.50 MB
|
|
Overcome PI Challenges on Perforated Power/Groung Planes
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.
セミナのプレゼンテーション 2012-01-19 |
PDF
2.30 MB
|
|
Overcome Signal Integrity Challenges in the multigigabit(s) Era
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.
セミナのプレゼンテーション 2011-12-15 |
PDF
781 KB
|
|
Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages
A day in the life of a Memory Architect.
セミナのプレゼンテーション 2011-10-24 |
PDF
1.86 MB
|
|
Signal Integrity Design Using Channel Simulation and EM Co-design
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables
セミナのプレゼンテーション 2010-04-21 |
|
|
Signal Integrity eSeminar Series Q&A: Being Successful with Fully Buffered DIMM (FBD) Designs
The following Questions and Answers were created from the live eSeminar broadcast of January 25, 2005. You can view the archived eSeminar by going to
セミナのプレゼンテーション 2005-01-25 |
PDF
60 KB
|
|
Solving Real World Jitter Problems for High-Speed Communications eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
53 KB
|
|
Successful High Speed Digital Design with ADS, EMPro, and SystemVue
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.
セミナのプレゼンテーション 2011-09-29 |
|
|
TDR vs. VNA Interconnect Characterization eSeminar FAQs
FAQs from the eSeminar
セミナのプレゼンテーション 2006-05-11 |
PDF
18 KB
|
|
Testing Receiver Jitter Tolerance eSeminar FAQs
Testing Receiver Jitter Tolerance eSeminar FAQs
セミナのプレゼンテーション 2006-06-14 |
PDF
50 KB
|
|
Why Do Measurement-based Channel Modeling?
Adobe .pdf of the paper presented at the High-Speed Digital Seminar, Ensuring MultiGigabit Design Success
セミナのプレゼンテーション 2008-01-20 |
PDF
3.62 MB
|
myAgilent に登録
製品登録
エンジニアリング・サービス