Discutez avec un expert

Digital Design & Interconnect Standards

Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.

Explore YouTube Videos 

1-10 of 10

Sort:
10 Reasons to Upgrade to a 16800 or 16900 Series Logic Analyzer 
10 Reasons to Upgrade to a 16800 or 16900 Series Logic Analyzer

Application Note 2007-12-03

8 Hints for Debugging and Validating High-speed Buses 
8 Hints for Debugging High-speed Buses

Application Note 2002-03-05

PDF PDF 2.24 MB
Debugging Parallel RapidIO Designs 

Application Note 2003-01-09

Designing and Validating High-Speed Memory Buses (AN 1382-2) 
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

Application Note 2001-12-20

Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems 
Application Note 1575

Application Note 2006-04-14

InfiniBand System Level Debugging (AN 1382-1) 
This application note is written for R & D engineers developing InfiniBand processors and InfiniBand system designers and integrators. It covers key concepts underlying system-level debug and validation of InfiniBand systems.

Application Note 2004-03-17

Passively Probing an InfiniBand System with an Agilent 16700 Series Logic Analysis System 
Passively Probing an InfiniBand with Agilent 16700 Series Logic Analysis System

Application Note 2004-03-05

PDF PDF 588 KB
Planning Your Design for Debug: FPGA Dynamic Probe 

Application Note 2005-01-26

Saving Time with Multiple-Channel Signal Integrity Measurements, (AN 1382-8) 
System complexity continues to grow exponentially. This results in more buses with more high-speed signals, which translates into more chances of signal integrity problems. Complex protocols, varying data payloads, and multiple operating modes create more opportunities for signal integrity to be...

Application Note 2002-03-14

Soft Touch Connectorless Logic Analyzer Probes 

Application Note 2011-03-14