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Digital Design & Interconnect Standards

Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.

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Accurate Calibration of Receiver Stress Test Signals for PCI Express® Rev. 3.0 
This paper describes the calibration of the receiver-stress signal according to the base specification of PCIe3. The calibration of the RX test signal is different from PCIe 2.0.

Application Note 2011-06-22

PDF PDF 4.82 MB
Languages 
Advanced Techniques for PCIe 3.0 Receiver Testing-Paper 
Advanced Techniques for PCIe 3.0 Receiver Testing-Paper

Application Note 2011-09-01

PDF PDF 2.20 MB
Automated PCI Express Receiver Compliance Test and Characterization with N5990A 
This product note shows how to use the test automation software platform to verify and debug your PCI Express bus designs. As an example, a multi-lane add-in card is used.

Application Note 2006-08-29

PDF PDF 444 KB
Automated USB 2.0 Receiver Compliance Test and Characterization with the Agilent N5990A 
Automated USB 2.0 Receiver Compliance Test and Characterization with the Agilent N5990A Software Platform: 8 pages

Application Note 2007-01-31

PDF PDF 272 KB
Benefits of using PCI Express 2.0. 
An overview of the main features and benefits of using PCI Express 2.0

Application Note 2008-10-17

PDF PDF 764 KB
Calibrated Jitter, Jitter Tolerance Test and Jitter Laboratory with the Agilent J-BERT N4903A 
This application note describes the N4903A BERT characterization solution for emerging serial gigabit devices: it helps engineers make quick and accurate jitter tolerance tests, which have been complicated and hard to do in the past.

Application Note 2006-07-18

PDF PDF 5.33 MB
Eye Characterization on Idle and Framed Data Traffic: the Bit Recovery Mode 
Traditionally, bit error rate testing compares the bits from a Device Under Test (DUT) against a reference data set, called the expected data. The user of Bit Error Ratio Tester (BERT) has to provide this expected data and load it into the tester.

Application Note 2005-09-21

PDF PDF 356 KB
Fast Total Jitter Test Solution 
This application note compares different total jitter measurement and extrapolation techniques to the Fast Total Jitter Measurement

Application Note 2005-08-29

PDF PDF 1.28 MB
Finding Sources of Jitter with Real-Time Jitter Analysis (AN 1448-2) 
This application note describes how to use a real-time oscilloscope with jitter analysis, along with the stimulus-response techniques, to meet the critical time-correlation requirement to relate jitter trend measurement results to measured signals.

Application Note 2003-06-30

PDF PDF 1.70 MB
Languages 
Flat Panel Display Link Test 
This Product Note shows how to verify the Bit Error Rate (BER) of 1-serial to 7-parallel Rx chip with the Agilent 81250 Parallel Bit Error Ratio Tester (ParBERT).

Application Note 2004-07-29

PDF PDF 128 KB
Languages 
Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-P 
This document describes the requirements for forward clocking topology RX Jitter tolerance testing.

Application Note 2009-03-24

PDF PDF 606 KB
HDMI Sink and Source Compliance Test and Characterization 
In this product note examples are given for advanced, automated HDMI compliance tests and characterization based on a high bandwidth oscilloscope, a TMDS Signal Generator and the Test Automation Software Platform.

Application Note 2006-10-27

PDF PDF 431 KB
Languages 
How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY) 
How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY)

Application Note 2007-07-30

PDF PDF 611 KB
How to Pass Receiver Test According to PCI Express® 3.0 CEM Specification 
This paper provides insight into the calibration method and tests, as well as the tools available. The biggest change between PCIe 2.x and rev. 3.0 is that RX test on cards will now be normative.

Application Note 2011-11-30

PDF PDF 3.22 MB
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How to use the Agilent 81200 together with Agilent VEE 
This attached Product Note shows how to use the Agilent 81200 Data Generator/Analyzer together with Agilent VEE for Signal Integrity Analysis.

Application Note 2002-01-28

PDF PDF 383 KB
Jitter Analysis Techniques for High Data Rates (AN 1432) 
This new application note describes the basic jitter measurements and the specific measurement techniques used in SONet/SDH/OTN and Gigabit Ethernet applications.

Application Note 2003-02-03

PDF PDF 4 MB
Languages 
Jitter Fundamentals: Jitter Tolerance Testing with Agilent ParBERT 81250 
This applicaiton note describes gain fast and efficient insight into the operation and performance of CDR, clock system and jitter tolerance.

Application Note 2003-12-02

PDF PDF 3.18 MB
Measuring Jitter in Digital Systems (AN 1448-1) 
Measuring jitter and how to calculate total jitter.

Application Note 2008-01-30

PDF PDF 1.91 MB
Measuring Jitter with the Agilent E4874A Characterization Software Components 
The Product Note shows how to measuring jitter with the Agilent E4874A Characterization Software Components on the Agilent 81200 Data Generator/Analyzer Platform. See also R & D Central at: http://www.agilent.com/find/randd Select "Bit Error Ratio Testing (BERT)" on that page. Then...

Application Note 2000-06-01

PDF PDF 102 KB
Method of Implementation (MOI) for DisplayPort 
Agilent Method of Implementation (MOI) for DisplayPort Sink Compliance Tests

Application Note 2007-11-03

PDF PDF 1.99 MB
Method of Implementation (MOI) for DisplayPort Sink Compliance Test 
Method of Implementation (MOI) for DisplayPort Sink Compliance Test

Application Note 2008-08-18

PDF PDF 1.87 MB
PCI Express Receiver Design Validation Test with 81134A / 81250A 
Describes functional validation and compliance and stress tests for PCI Express receiver design

Application Note 2005-03-18

PDF PDF 2.01 MB
Languages 
PCI Express® Revision 2 - Receiver Testing With J-BERT N4903A and 81150A Pulse 

Application Note 2008-12-03

PDF PDF 1000 KB
PCIe Revision 2 Receiver Jitter Tolerance Testing with J-BERT N4903B  
This document focuses on physical layer testing of the transmitter (TX) and receiver (RX) ports of PCI EXPRESS® (PCIe) devices.

Application Note 2006-01-30

PDF PDF 1.31 MB
Languages 
Upgrade to PCI Express 2.0© Receiver Test 
The 15431A is a filter set for the 81150A. It generates the random jitter profile for testing PCI Express 2.0 receivers, to be used in conjunction with the N4903A. This fact sheet explains the upgrade.

Application Note 2008-10-24

PDF PDF 348 KB

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