Design and Simulation of High-Speed Digital
Agilent tools provide views into the time and frequency domains, revealing the underlying problems and ensuring compliant designs. With Agilent, you'll achieve your best design.
High Speed Digital Design Challenges
- Analyzing complete chip-to-chip links by co-simulating individual components, each at its most appropriate level of abstraction: channel-, circuit- or physical-level
- Importing backplane S-parameter models accurately into circuit and channel simulations, avoiding causality and passivity issues
- Correlating measured and simulated data before using simulation to interpolate between measurement planes and extrapolating to virtual prototypes
What's New
- ClioSoft Announces the Integration of SOS Design Data Management with Advanced Design System
- Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
- Agilent Technologies to Demonstrate Newest High-Speed Digital Design and Test Solutions at DesignCon
- Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links
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1-14 of 14
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Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
Application Note 2001-12-20 |
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1.51 MB
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Designing High Speed Backplanes Utilizing Physical Layer Test System
This Application Note focuses on the problems introduced into the backplane assembly design by the many linear passive components that create reflections due to impedance discontinuities.
Application Note 2006-01-18 |
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Effective Reflection Characterization for Active Devices Using ENA Option TDR Application Note
This application note describes Hot TDR measurement, which is an effective characterization method for the reflection of transmitter and receiver.
Application Note 2012-01-12 |
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416 KB
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Explore the SERDES Design Space Using the IBIS AMI Channel Simulation Flow
Simulation of modern chip-to-chip links requires you abandon the SPICE-based approach and adopt a new approach based on an IBIS AMI channel simulation flow.
Application Note 2012-09-21 |
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467 KB
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Frequency Domain Analysis of Jitter Amplification in Clock Channels
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained.
Application Note 2012-11-01 |
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257 KB
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Limitations and Accuracies of Time and Frequency Domain Analysis of Physical Layer Devices
Application Note 2005-11-01 |
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2.83 MB
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Signal Integrity Analysis Series Part 1: Single-Port TDR, TDR/TDT, & 2-Port TDR
This Application Note focuses on part 1: those which use a single-port TDR, those which use TDR/TDT, and those which use 2-port TDR.
Application Note 2007-01-01 |
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3.50 MB
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Signal Integrity Analysis Series Part 2: 4-Port TDR/VNA/PLTS
This Application Note focuses on part 2: those which use a 4-port TDR/VNA/PLTS.
Application Note 2007-02-21 |
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2.75 MB
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Signal Integrity Analysis Series Part 3: The ABCs of De-Embedding
This Application Note focuses on Part 3: The ABCs of De-Embedding explaining different de-embedding techniques & shows how to minimize fixture effects for best results.
Application Note 2007-07-01 |
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2.44 MB
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Simulating FPGA Power Integrity Using S-Parameter Models
This application note describes how self-impedance (frequency) can easily be determined by simulating the frequency domain self-impedance profile of a Power Distribution Network (PDN).
Application Note 2012-04-02 |
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5.68 MB
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Simulating High-Speed Serial Channels with IBIS-AMI Models
This paper reviews some of the benefits and limitations of using IBIS models and introduces the new AMI extensions to the latest IBIS version 5.0 specification.
Application Note 2011-11-15 |
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Using ADS for Signal Integrity Optimization
This white paper shows how to replace a multi-dimensional sweep of a long running PRBS time-domain simulation (including manual data evaluation) by short, channel-pulse characterization in the Advanced Design System to efficiently optimize a channel.
Application Note 2009-10-19 |
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275 KB
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Using Clock Jitter Analysis to Reduce BER in Serial Data Applications
This Application Note emphasizes on the emerging techniques for reference clock jitter analysis from the perspective of oscillator physics, phase noise theory, and serial data technology.
Application Note 2006-12-01 |
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1.15 MB
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Which Electromagnetic Simulator Should I Use?
This paper outlines three of the key EM simulation technologies, MoM, FEM, FDTD and attempt to compare and contrast the relative merits of each.
Application Note 2012-04-06 |
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3.21 MB
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