Design and Simulation of High-Speed Digital
Agilent tools provide views into the time and frequency domains, revealing the underlying problems and ensuring compliant designs. With Agilent, you'll achieve your best design.
High Speed Digital Design Challenges
- Analyzing complete chip-to-chip links by co-simulating individual components, each at its most appropriate level of abstraction: channel-, circuit- or physical-level
- Importing backplane S-parameter models accurately into circuit and channel simulations, avoiding causality and passivity issues
- Correlating measured and simulated data before using simulation to interpolate between measurement planes and extrapolating to virtual prototypes
What's New
- ClioSoft Announces the Integration of SOS Design Data Management with Advanced Design System
- Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
- Agilent Technologies to Demonstrate Newest High-Speed Digital Design and Test Solutions at DesignCon
- Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links
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Digital and Photonics Webcast Series
Originally broadcast 2010, 2011. Access the recordings of many broadcasts
Webcast - recorded |
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Digital Webcast Series - Master the high-speed digital test challenge
multiple broadcasts - refer to www.agilent.com/find/DPTwebcasts for the complete list
Webcast - recorded |
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High-Sensitivity Current Measurements using an Oscilloscope Webcast
Original broadcast April 17, 2013
Webcast - recorded |
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Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.
Webcast - recorded |
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Using IBIS AMI Models as ‘Executable Data sheets’ in High Speed Digital Interconnect Simulations
Originally broadcast Sept 9, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.
Webcast - recorded |
