聯絡安捷倫專家

鎖相迴路

安捷倫提供完整的設計及模擬工具,讓您能夠輕鬆設計、合成和模擬鎖相迴路及頻率合成器,確保您可以達成重要效能目標並製造可靠的元件。利用安捷倫的電子設計自動化軟體,例如 ADS、GoldenGate RFIC模擬器或 Genesys,您可偵測安定時間和相位雜訊等重要特性,並將其最佳化,以獲致優異效能。

完成設計後,則可利用安捷倫的信號源分析儀、示波器及頻譜分析儀等量測儀器,快速量測並驗證您的設計原形與產品。

Agilent E5052B SSA信號源分析儀可針對PLL/VCO設計與製造,執行快速而準確的量測,並可在更短時間內,將高品質、高獲利產品推出上市。無論您是需要量測相位雜訊、調幅雜訊、鎖定時間、VCO調諧效能、諧波雜訊或是直流雜訊,安捷倫EDA軟體讓您一次搞定所有問題。

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Presentation on Simulating Phase Locked Loops using ADS 
This Presentation details PLL simulation using ADS, Envelope simulation, PLL component behavioral modeling, Phase noise, Spurs, Fractional N-simulation and Divide ratio using sigma delta modulator.

研討會講義 2010-08-19

PDF PDF 1 MB
Agilent EEsof EDA Customer Education and Services 
Brief overview of Agilent EEsof EDA Customer Education and Services.

訓練教材 2010-08-11

 
Presentation on Trends in Signal Integrity Tests 
A joint Presentation presented by Michael Reser and Rainer Plitschka (Agilent Technologies) on parametric tests for high-speed serial technologies focusing on latest trends in Signal Integrity tests.

訓練教材 2006-09-01

PDF PDF 2.13 MB
Making Early Design Tradeoffs using Advanced Measurement Based Behavioral Models 
This Presentation (Connecting Design and Test Seminar, paper #2) decribes early design tradeoffs using advanced measurement based behavioral models in detail.

研討會講義 2003-05-29

PDF PDF 2.22 MB
Presentation on ADS for Wireline and High Speed Analog Design 
A detailed Presentation (presented on 21 May 2002) on using Advanced Design System for Wireline and High Speed Analog Design.

研討會講義 2002-05-21

PDF PDF 4.75 MB
A Practical Approach to Verifying RFICs with Fast Mismatch Analysis 
Originally broadcast October 28, 2010

網路廣播 -- 存檔

 
Successful Modulation Analysis in 3 Steps Webcast 
Original broadcast January 22, 2014

網路廣播 -- 存檔

 
Genesys Webcasts - "How-To-Design" series  
Originally broadcast in 2009. Access the 6 WebEX recordings

網路廣播 -- 存檔