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Phase-Locked Loops (PLL)

Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.

After your design is complete, Agilent's test and measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.

The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution. 

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2014 Agilent EEsof EDA Training Course Calendar 
Scheduled Agilent EEsof courses for the United States and Canada

Classroom Training

 
Agilent EEsof EDA Customer Education and Services 
Brief overview of Agilent EEsof EDA Customer Education and Services.

Training Materials 2010-08-11

 
Ethernet Compliance Testing: Become More Green and Energy Efficient Webcast 
Original broadcast March 20, 2013

Webcast - recorded

 
Presentation on Simulating Phase Locked Loops using ADS 
This Presentation details PLL simulation using ADS, Envelope simulation, PLL component behavioral modeling, Phase noise, Spurs, Fractional N-simulation and Divide ratio using sigma delta modulator.

Seminar Materials 2010-08-19

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