DDR Memory Design & Test
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today – the original DDR (also called DDR1), DDR2 which improved performance and lowered power consumption, DDR3 with even better performance, and low-power DDR (LPDDR), that is targeted for mobile devices.
Agilent is an active member of JEDEC, with consistent participation in workshops and specification issues. These resources you find here will provide you with an overview of DDR design, understand the latest measurement techniques, and illustrate design and debug approaches.
Use the matrix below to discover specific solutions for your DDR needs.
|Simulation||Functional Test (Oscilloscope)||Validation (Logic Analyzers)||Probing Solutions|
|DDR2||Learn more||Learn more||Learn more||Learn more|
|DDR3||Learn more||Learn more||Learn more||Learn more|
|DDR4||Planned||Learn more||Learn more|
|LPDDR2||Learn more||Learn more||Learn more|
|LPDDR3||Planned||Learn more||Learn more|
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A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.
Application Note 2008-09-10
Crossing the Digital-Analog Divide - White Paper
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.
Application Note 2012-05-02
PDF 6.46 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
Application Note 2001-12-20
Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems
Application Note 1575
Application Note 2006-04-14