鎖相迴路
安捷倫提供完整的設計及模擬工具,讓您能夠輕鬆設計、合成和模擬鎖相迴路及頻率合成器,確保您可以達成重要效能目標並製造可靠的元件。利用安捷倫的電子設計自動化軟體,例如 ADS、GoldenGate RFIC模擬器或 Genesys,您可偵測安定時間和相位雜訊等重要特性,並將其最佳化,以獲致優異效能。
完成設計後,則可利用安捷倫的信號源分析儀、示波器及頻譜分析儀等量測儀器,快速量測並驗證您的設計原形與產品。
Agilent E5052B SSA信號源分析儀可針對PLL/VCO設計與製造,執行快速而準確的量測,並可在更短時間內,將高品質、高獲利產品推出上市。無論您是需要量測相位雜訊、調幅雜訊、鎖定時間、VCO調諧效能、諧波雜訊或是直流雜訊,安捷倫EDA軟體讓您一次搞定所有問題。
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DesignGuides: Expert Help in the Time-to-Market Race
Agilent EEsof EDA DesignGuides data sheet
產品型錄 1999-07-01 |
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Designing to Digital Wireless Specifications using Circuit Envelope Simulation
This Paper by How-Siang Yap discusses the Circuit Envelope technology developed specifically to simulate modern wireless circuits with complex digitally modulated RF signals such as CDMA and TDMA.
技術總覽 1998-06-01 |
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PLL FM-Modulator Suitable for Mobile and Radio Communication Simulation
This Technical Overview details a new PLL-FM Modulator with rapid acquisition time about 1000 times less than the conventional PLL with less spurs which is suitable in mobile and radio communications.
技術總覽 2001-10-31 |
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