Phase-Locked Loops (PLL)
Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.
After your design is complete, Agilent's test and measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.
The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution.
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DesignGuides: Expert Help in the Time-to-Market Race
Agilent EEsof EDA DesignGuides data sheet
Data Sheet 1999-07-01 |
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Designing to Digital Wireless Specifications using Circuit Envelope Simulation
This Paper by How-Siang Yap discusses the Circuit Envelope technology developed specifically to simulate modern wireless circuits with complex digitally modulated RF signals such as CDMA and TDMA.
Technical Overview 1998-06-01 |
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PLL FM-Modulator Suitable for Mobile and Radio Communication Simulation
This Technical Overview details a new PLL-FM Modulator with rapid acquisition time about 1000 times less than the conventional PLL with less spurs which is suitable in mobile and radio communications.
Technical Overview 2001-10-31 |
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