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PCIe 2.0/3.0, PCI Express® Design & Test Information Resource Center

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

Regardless of the PCIe generation design challenges you are facing, Agilent offers a complete solution set from electrical to protocol. Work with Agilent and achieve your best design.

See Measurement Solution Examples: PCIe 3.0 Transmitter Test    PCIe 3.0 Receiver Test

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Accurate Calibration of Receiver Stress Test Signals for PCI Express® Rev. 3.0 
This paper describes the calibration of the receiver-stress signal according to the base specification of PCIe3. The calibration of the RX test signal is different from PCIe 2.0.

Application Note 2011-06-22

Advanced Techniques for PCIe 3.0 Receiver Testing-Paper 
Advanced Techniques for PCIe 3.0 Receiver Testing-Paper

Application Note 2011-09-01

PDF PDF 2.20 MB
Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-P 
This document describes the requirements for forward clocking topology RX Jitter tolerance testing.

Application Note 2009-03-24

PDF PDF 606 KB
How to Pass Receiver Test According to PCI Express® 3.0 CEM Specification 
This paper provides insight into the calibration method and tests, as well as the tools available. The biggest change between PCIe 2.x and rev. 3.0 is that RX test on cards will now be normative.

Application Note 2011-11-30

PCI Express Receiver Design Validation Test with 81134A / 81250A 
Describes functional validation and compliance and stress tests for PCI Express receiver design

Application Note 2005-03-18

PCI Express Transmitter Electrical Validation and Compliance Testing - Application Note 
This application note is intended for digital designers and developers validating electrical performance of PCI Express-based designs and working toward electrical compliance of PCI Express products.

Application Note 2011-10-28

PDF PDF 1.01 MB
PCI Express® Revision 2 - Receiver Testing With J-BERT N4903A and 81150A Pulse 

Application Note 2008-12-03

PDF PDF 1000 KB
PCIe Revision 2 Receiver Jitter Tolerance Testing with J-BERT N4903B  
This document focuses on physical layer testing of the transmitter (TX) and receiver (RX) ports of PCI EXPRESS® (PCIe) devices.

Application Note 2006-01-30

Upgrade to PCI Express 2.0© Receiver Test 
The 15431A is a filter set for the 81150A. It generates the random jitter profile for testing PCI Express 2.0 receivers, to be used in conjunction with the N4903A. This fact sheet explains the upgrade.

Application Note 2008-10-24

PDF PDF 348 KB