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PCIe 2.0/3.0, PCI Express® Design & Test Information Resource Center

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

Regardless of the PCIe generation design challenges you are facing, Agilent offers a complete solution set from electrical to protocol. Work with Agilent and achieve your best design.

See Measurement Solution Examples: PCIe 3.0 Transmitter Test    PCIe 3.0 Receiver Test

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Evénements Agilent en France 
Bienvenue sur la page des événements auxquels participe Agilent en France

Seminar

 
Automate Multilane Gigabit Oscilloscope Testing with Switch Matrix Webcast 
Original broadcast November 20, 2013

Webcast - recorded

 
DesignCon 2014 
Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD

Tradeshow

 
EMC Back to Basics Webcast 
Original broadcast April 16, 2014

Webcast - recorded

 
Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

Webcast - recorded

 
Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

Webcast - recorded

 
Keeping up with 10G USB 3.1 Physical Layer Test Challenges Webcast 
Original broadcast January 15, 2014

Webcast - recorded

 
Navigating Compliance Standards Panel Discussion 
Original broadcast July 17, 2013

Webcast - recorded

 
Network Analysis Back to Basics Webcast 
Recorded broadcast August 21, 2013

Webcast

 
Network Analysis Basics for High Speed Digital Engineers Webcast 
Original broadcast July 30, 2013

Webcast - recorded

 
Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

Webcast - recorded

 
PCI Express 3.0 How to pass receiver compliance test for add-in cards and motherboards - webcast 
Original broadcast October 27, 2011

Webcast - recorded

 
PCI Express 3.0 Receiver test of ASICs- how to face this challenge - webcast 
When PCIe 3.0 was generated, it was a goal to re-use the existing passive infrastructure - the channels. With nearly double the signal rate (8Gb/s vs. 5Gb/s), the error free transmission now heavily depends on the RX. Therefore it is now normati...

Webcast - recorded

 
PCIe™ 3.0 Receiver Testing: How to Generate the Test Set-up and Calibrate the Stressed Eye 
Originally broadcast October 12, 2010

Webcast - recorded

 
Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs 
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

Webcast - recorded

 
Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

Webcast - recorded

 
Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Live broadcast May 22, 2014; 10am PT/1pm ET

Webcast

 
Test & Measurement events in Europe, Middle East & Africa 
Test & Measurement events in Europe, the Middle East, and Africa - seminars, trade shows, user group meetings, webcasts, tutorials and conferences.

Seminar