DDR 存储器设计和测试
双数据速率（DDR）同步动态随机存取存储器（SDRAM）现在有多种形式，其中包括最原始的 DDR（也称为 DDR1）；性能更高、功耗更低的 DDR2；具有更佳性能的 DDR3；以及面向移动器件的低功率 DDR （LPDDR）。
安捷伦是 JEDEC 的积极成员，一直以来都在积极参与研讨会和相关标准等问题。您在此找到的这些资源将使您能够概括地认识 DDR 设计，帮助您了解最新的测量技术，并为您讲解设计和调试方法。
去除所有优化1-12 / 12
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改善查看周期:调试DDR和DD2系统中的间歇
应用说明 2006-05-01 |
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A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate
synchronous dynamic random access memory) signals.
应用说明 2008-09-10 |
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Crossing the Digital-Analog Divide - White Paper
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.
应用说明 2012-05-02 |
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6.46 MB
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DDR Memory Overview, Development Cycle, and Challenges - Technical Overview
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.
应用说明 2012-12-14 |
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1.37 MB
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DDR Probing for Physical Layer and Functional Testing
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.
应用说明 2008-12-19 |
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617 KB
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DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
应用说明 2013-01-24 |
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1.65 MB
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Debugging Signal Integrity and Protocol Layers on DDR Designs
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.
应用说明 2008-12-19 |
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984 KB
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Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
应用说明 2001-12-20 |
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1.51 MB
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Ensuring Compliance and Interoperability of DDR Designs
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.
应用说明 2008-12-19 |
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379 KB
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Find and identify the causes of data corruption and elusive failures
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.
应用说明 2008-12-19 |
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360 KB
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Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.
应用说明 2012-01-31 |
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1.40 MB
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Separating Read/Write Signals for DDR DRAM and Controller Validation
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.
应用说明 2008-12-19 |
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805 KB
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