DDR Memory Design & Test
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today – the original DDR (also called DDR1), DDR2 which improved performance and lowered power consumption, DDR3 with even better performance, and low-power DDR (LPDDR), that is targeted for mobile devices.
Agilent is an active member of JEDEC, with consistent participation in workshops and specification issues. These resources you find here will provide you with an overview of DDR design, understand the latest measurement techniques, and illustrate design and debug approaches.
Use the matrix below to discover specific solutions for your DDR needs.
| Simulation | Functional Test (Oscilloscope) | Validation (Logic Analyzers) | Probing Solutions | |
|---|---|---|---|---|
| DDR2 | Learn more | Learn more | Learn more | Learn more |
| DDR3 | Learn more | Learn more | Learn more | Learn more |
| DDR4 | Planned | Learn more | Learn more | |
| LPDDR2 | Learn more | Learn more | Learn more | |
| LPDDR3 | Planned | Learn more | Learn more | |
| GDDRS | Planned | Learn more | ||
| UFS | Learn more |
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A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate
synchronous dynamic random access memory) signals.
Application Note 2008-09-10 |
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