DDR 記憶體設計與測試
今日的雙倍資料速率 (DDR) 同步動態隨機存取記憶體 (SDRAM) 具有多種形式，包括原始的 DDR (也稱為 DDR1)、改善效能且降低功耗的 DDR2、效能更佳的 DDR3，以及用於行動裝置的低功率 DDR (LPDDR)。
安捷倫為 JEDEC 成員，積極參與 研習營及規格制訂的討論。 本頁面提供之資源可協助您認識DDR設計、了解最新的量測技巧，並說明設計與除錯方式。
請利用下方表格尋找符合您 DDR 需求的特定解決方案
| 模擬 |
功能測試 (示波器) |
驗證 (邏輯分析儀) |
探量解決方案 | |
|---|---|---|---|---|
| DDR2 | 詳細資訊 | 詳細資訊 | 詳細資訊 | 詳細資訊 |
| DDR3 | 詳細資訊 | 詳細資訊 | 詳細資訊 | 詳細資訊 |
| DDR4 | 規劃中 | 詳細資訊 | 詳細資訊 | |
| LPDDR2 | 詳細資訊 | 詳細資訊 | 詳細資訊 | |
| LPDDR3 | 規劃中 | 詳細資訊 | 詳細資訊 | |
| GDDRS | 規劃中 | 詳細資訊 |
移除所有細分1-12 / 12
|
A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate
synchronous dynamic random access memory) signals.
應用手冊 2008-09-10 |
|
|
Crossing the Digital-Analog Divide - White Paper
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.
應用手冊 2012-05-02 |
PDF
6.46 MB
|
|
DDR Memory Overview, Development Cycle, and Challenges - Technical Overview
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.
應用手冊 2012-12-14 |
PDF
1.37 MB
|
|
DDR Probing for Physical Layer and Functional Testing
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.
應用手冊 2008-12-19 |
PDF
617 KB
|
|
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
應用手冊 2013-01-24 |
PDF
1.65 MB
|
|
Debugging Signal Integrity and Protocol Layers on DDR Designs
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.
應用手冊 2008-12-19 |
PDF
984 KB
|
|
Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
應用手冊 2001-12-20 |
PDF
1.51 MB
|
|
Ensuring Compliance and Interoperability of DDR Designs
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.
應用手冊 2008-12-19 |
PDF
379 KB
|
|
Find and identify the causes of data corruption and elusive failures
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.
應用手冊 2008-12-19 |
PDF
360 KB
|
|
Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems
Application Note 1575
應用手冊 2006-04-14 |
|
|
Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.
應用手冊 2012-01-31 |
PDF
1.40 MB
|
|
Separating Read/Write Signals for DDR DRAM and Controller Validation
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.
應用手冊 2008-12-19 |
PDF
805 KB
|
註冊myAgilent
註冊您的產品
為何選擇向安捷倫採購