DDR Memory Design & Test
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today – the original DDR (also called DDR1), DDR2 which improved performance and lowered power consumption, DDR3 with even better performance, and low-power DDR (LPDDR), that is targeted for mobile devices.
Agilent is an active member of JEDEC, with consistent participation in workshops and specification issues. These resources you find here will provide you with an overview of DDR design, understand the latest measurement techniques, and illustrate design and debug approaches.
Use the matrix below to discover specific solutions for your DDR needs.
| Simulation | Functional Test (Oscilloscope) | Validation (Logic Analyzers | Probing Solutions | |
|---|---|---|---|---|
| DDR2 | Learn more | Learn more | Learn more | Learn more |
| DDR3 | Learn more | Learn more | Learn more | Learn more |
| DDR4 | Planned | Learn more | Learn more | |
| LPDDR2 | Learn more | Learn more | Learn more | |
| LPDDR3 | Planned | Learn more | Learn more | |
| GDDRS | Planned | Learn more |
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A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate
synchronous dynamic random access memory) signals.
어플리케이션 노트 2008-09-10 |
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Crossing the Digital-Analog Divide - White Paper
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.
어플리케이션 노트 2012-05-02 |
PDF
6.46 MB
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DDR Memory Overview, Development Cycle, and Challenges - Technical Overview
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.
어플리케이션 노트 2012-12-14 |
PDF
1.37 MB
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DDR Probing for Physical Layer and Functional Testing
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.
어플리케이션 노트 2008-12-19 |
PDF
617 KB
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DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
어플리케이션 노트 2013-01-24 |
PDF
1.65 MB
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Debugging Signal Integrity and Protocol Layers on DDR Designs
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.
어플리케이션 노트 2008-12-19 |
PDF
984 KB
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Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
어플리케이션 노트 2001-12-20 |
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1.51 MB
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Ensuring Compliance and Interoperability of DDR Designs
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.
어플리케이션 노트 2008-12-19 |
PDF
379 KB
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Find and identify the causes of data corruption and elusive failures
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.
어플리케이션 노트 2008-12-19 |
PDF
360 KB
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Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems
Application Note 1575
어플리케이션 노트 2006-04-14 |
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Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.
어플리케이션 노트 2012-01-31 |
PDF
1.40 MB
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Separating Read/Write Signals for DDR DRAM and Controller Validation
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.
어플리케이션 노트 2008-12-19 |
PDF
805 KB
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