DDR 記憶體設計與測試
今日的雙倍資料速率 (DDR) 同步動態隨機存取記憶體 (SDRAM) 具有多種形式，包括原始的 DDR (也稱為 DDR1)、改善效能且降低功耗的 DDR2、效能更佳的 DDR3，以及用於行動裝置的低功率 DDR (LPDDR)。
安捷倫為 JEDEC 成員，積極參與 研習營及規格制訂的討論。 本頁面提供之資源可協助您認識DDR設計、了解最新的量測技巧，並說明設計與除錯方式。
請利用下方表格尋找符合您 DDR 需求的特定解決方案
| 模擬 |
功能測試 (示波器) |
驗證 (邏輯分析儀) |
探量解決方案 | |
|---|---|---|---|---|
| DDR2 | 詳細資訊 | 詳細資訊 | 詳細資訊 | 詳細資訊 |
| DDR3 | 詳細資訊 | 詳細資訊 | 詳細資訊 | 詳細資訊 |
| DDR4 | 規劃中 | 詳細資訊 | 詳細資訊 | |
| LPDDR2 | 詳細資訊 | 詳細資訊 | 詳細資訊 | |
| LPDDR3 | 規劃中 | 詳細資訊 | 詳細資訊 | |
| GDDRS | 規劃中 | 詳細資訊 |
1-25 / 26
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DDR4 Memory Bus Protocol Analysis - FuturePlus
DDR4 Memory Bus Protocol Analysis from FuturePlus and Agilent.
解決方案簡介 2013-01-26 |
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DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
應用手冊 2013-01-24 |
PDF
1.65 MB
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DDR Memory Design and Test – A Better Way
Agilent offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.
型錄 2012-12-19 |
PDF
5.17 MB
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DDR Memory Design and Test Overview
Brief overview of Agilent solutions for DDR design and test.
型錄 2012-12-19 |
PDF
1.14 MB
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DDR Memory Overview, Development Cycle, and Challenges - Technical Overview
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.
應用手冊 2012-12-14 |
PDF
1.37 MB
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B4621B for DDR2, DDR3, or DDR4 Debug and Validation - Data Sheet
The B4621B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for double- edge data-rate captures up to 2.5Gb/s.
產品型錄 2012-09-04 |
PDF
1.32 MB
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B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.
產品型錄 2012-09-03 |
PDF
1.03 MB
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準確執行記憶體量測的技巧 - 系列影片
這一系列影片教導使用者如何在更短的時間內，完成一連串完整、獨特且深入的分析。
基本展示 2012-05-28 |
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Crossing the Digital-Analog Divide - White Paper
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.
應用手冊 2012-05-02 |
PDF
6.46 MB
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Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.
應用手冊 2012-01-31 |
PDF
1.40 MB
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Agilent Technologies Introduces Industry's Fastest Logic Analyzer
New Instrument Offers Reliable Data Capture Rates up to 4 Gb/s on Industry's Smallest Eye Openings
新聞資料 2011-03-28 |
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Agilent Technologies Introduces Industry-First, Most Comprehensive DDR3 Test Suite
新聞資料 2009-04-30 |
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Agilent Technologies to Participate as Sole Test, Measurement Expert at JEDEC Flash Storage Summits
新聞資料 2009-04-30 |
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Separating Read/Write Signals for DDR DRAM and Controller Validation
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.
應用手冊 2008-12-19 |
PDF
805 KB
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DDR Probing for Physical Layer and Functional Testing
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.
應用手冊 2008-12-19 |
PDF
617 KB
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Ensuring Compliance and Interoperability of DDR Designs
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.
應用手冊 2008-12-19 |
PDF
379 KB
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Find and identify the causes of data corruption and elusive failures
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.
應用手冊 2008-12-19 |
PDF
360 KB
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Debugging Signal Integrity and Protocol Layers on DDR Designs
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.
應用手冊 2008-12-19 |
PDF
984 KB
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A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate
synchronous dynamic random access memory) signals.
應用手冊 2008-09-10 |
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Jitter Solutions for Telecom, Enterprise, and Digital Designs
Complete solutions for characterization and test of jitter in high-speed digital transmission systems, high-speed I/O connections, and buses.
型錄 2008-06-25 |
PDF
3.49 MB
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Industry's First DDR2, DDR3 BGA Probe Solution for Oscilloscopes, Logic Analyzers
Industry's First DDR2, DDR3 BGA Probe Solution for Oscilloscopes, Logic Analyzers
新聞資料 2008-01-30 |
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DDR 1, 2 and 3 solutions Video
Includes probing methods, read/write separation technique and automated JEDEC compliance measurements with Infiniium Series oscilloscopes.
基本展示 2007-12-27 |
WMF
52.75 KB
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Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems
Application Note 1575
應用手冊 2006-04-14 |
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Probe loading
Probe loading
基本展示 2005-12-22 |
WMF
19.66 MB
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Flexibility of Agilent's InfiniiMax Probe System
This 10-minute video provides some very practical
產品導覽 2004-11-22 |
WMF
20.29 MB
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