Phase-Locked Loops (PLL)
Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.
After your design is complete, Agilent's test and measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.
The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution.
상세분류 제거1-10 / 10
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Analyzing Phase-Locked Loop Capture and Tracking Range (AN 358-13)
This Application Note is for information only. Agilent no longer sells or supports these products.
어플리케이션 노트 1990-10-01 |
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667 KB
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Analyzing Phase-Locked Loop Transients in the Modulation Domain (AN 358-7)
This Application Note is for information only. Agilent no longer sells or supports these products.
어플리케이션 노트 1989-10-01 |
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658 KB
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Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluation
This application note describes introduces practical solutions for VCO/PLL performance evaluation and gives actual examples of parameter measurements using the E5052B.
어플리케이션 노트 2008-11-21 |
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Characterizing phase-locked-loop signal transition behaviors of Microphonic/Phase-hit
This paper discusses how Agilent's Signal Source Analyzer helps you to identify unwanted phase-locked-loop transition "phase-hits", and achieve easy, comprehensive and accurate phase-locked-loop characterization in both linear and nonlinear regions.
어플리케이션 노트 2008-10-02 |
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Design and Measurement of a 400 MHz Frequency Synthesizer: Accuracy Proof
This Application Note explains the 400 MHz PLL design with examples and hence giving the engineer a powerful effective tool for designing real PLLs.
어플리케이션 노트 2001-11-01 |
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Optimizing VCO/PLL evaluations and PLL synthesizer designs AN 1330-1
This application note clarifies the role and performance requirements of the synthesized oscillator used in wireless communication equipment, and introduces our test solution for VCO/PLL evaluation.
어플리케이션 노트 2000-09-01 |
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1.04 MB
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PLL’s using a Charge Pump, High Divide-by-N Factors, and Decimation before Plotting
This Application Note shows an approach for designing a phase locked loop (PLL) that uses a charge pump, High Divide-by-N Factors, and Decimation before Plotting.
어플리케이션 노트 2001-03-20 |
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Simplified Analysis of Phase-Locked Loop Capture and Tracking Range (AN 1200-7)
The Agilent 53310A's ability to measure and display a signal's continuous frequency over time makes dynamic frequency analysis of PLLs easy. A direct measure of the PLL's capture and tracking range is obtained by monitoring the output frequency while the PLL is forced to go in and out of lock. A...
어플리케이션 노트 2000-08-01 |
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The RC Charge Pump: A Versatile RF Library circuit for PLL’s and Beyond
This Application Note describes the RC Charge Pump; a Versatile RF Library circuit for Phase Locked Loops (PLL’s). Logic gate delays and a diode amplitude demodulator are also possible with this charge-pump.
어플리케이션 노트 1998-03-19 |
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941 KB
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What is ADS able to simulate concerning PLLs? (login required)
This page covers simulating phase-locked loops using Advanced Design System (ADS).
어플리케이션 노트 2011-03-15 |
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