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Phase-Locked Loops (PLL)
Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.
After your design is complete, Agilent's test and measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.
The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution.
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- 81160A Pulse Function Arbitrary Noise Generator (2)
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- 81130A Pulse Data Generator, 400/660 MHz and 1.32 Gb/s (2)
- 81133A Pulse Pattern Generator, 3.35 GHz, single channel (2)
- 81134A Pulse Pattern Generator, 3.35 GHz, dual-channel (2)
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- 81250 7 Gb/s ParBERT Modules (N4874A, N4875A) (2)
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- PCI Express® Gen 2.0 RX jitter testing with J-BERT N4903B (2)
- N4903B J-BERT high-performance serial BERT up to 7 Gb/s and 12.5 Gb/s with complete jitter tolerance (4)
- 81150A Pulse Function Arbitrary Noise Generator (2)
- N2102B PXIT Pattern Generator (2)
- 81250 675 Mb/s ParBERT Modules (E4832A, E4835A, E4838A) (2)
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Data Generators & Analyzers
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Generators, Sources, Supplies
1-4 of 4
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Agilent Veranstaltungs-Webseite für Deutschland
Willkommen zur neuen Agilent Veranstaltungs-Webseite für Deutschland
Seminar |
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PCI Express(R) 3.0 Strategies for Transmitter and Receiver Validation
Originally broadcast Feb 10, 2011
Webcast - recorded |
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Test & Measurement events in Europe, Middle East & Africa
Test & Measurement events in Europe, the Middle East, and Africa - seminars, trade shows, user group meetings, webcasts, tutorials and conferences.
Seminar |
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USB 3.0 Physical Layer Test Challenges: Gen3 and Beyond Webcast
Live broadcast June 13, 2013; 10am Pacific / 1pm Eastern
Webcast |
