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Phase-Locked Loops (PLL)

Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.

After your design is complete, Agilent's electronic measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.

The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution. 

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Presentation on Simulating Phase Locked Loops using ADS 
This Presentation details PLL simulation using ADS, Envelope simulation, PLL component behavioral modeling, Phase noise, Spurs, Fractional N-simulation and Divide ratio using sigma delta modulator.

Seminar Materials 2010-08-19

PDF PDF 1 MB
Agilent EEsof EDA Customer Education and Services 
Brief overview of Agilent EEsof EDA Customer Education and Services.

Training Materials 2010-08-11

 
SSA presentation material – customer viewable slides with speaker notes 

Seminar Materials 2008-10-10

PDF PDF 1.01 MB
Characterizing phase-locked-loop signal transition behaviors such as microphonic/phase-hits 

Seminar Materials 2008-10-10

PDF PDF 1.26 MB
Presentation on Trends in Signal Integrity Tests 
A joint Presentation presented by Michael Reser and Rainer Plitschka (Agilent Technologies) on parametric tests for high-speed serial technologies focusing on latest trends in Signal Integrity tests.

Training Materials 2006-09-01

PDF PDF 2.13 MB
Making Early Design Tradeoffs using Advanced Measurement Based Behavioral Models 
This Presentation (Connecting Design and Test Seminar, paper #2) decribes early design tradeoffs using advanced measurement based behavioral models in detail.

Seminar Materials 2003-05-29

PDF PDF 2.22 MB
Understanding Jitter and Wander Measurements and Standards, Second Edition 

Training Materials 2003-02-01

PDF PDF 6.18 MB
Presentation on ADS for Wireline and High Speed Analog Design 
A detailed Presentation (presented on 21 May 2002) on using Advanced Design System for Wireline and High Speed Analog Design.

Seminar Materials 2002-05-21

PDF PDF 4.75 MB
2014 Agilent EEsof EDA Training Course Calendar 
Scheduled Agilent EEsof courses for the United States and Canada

Classroom Training

 
Successful Modulation Analysis in 3 Steps Webcast 
Original broadcast January 22, 2014

Webcast - recorded

 
Genesys Webcasts - "How-To-Design" series  
Originally broadcast in 2009. Access the 6 WebEX recordings

Webcast - recorded

 
A Practical Approach to Verifying RFICs with Fast Mismatch Analysis 
Originally broadcast October 28, 2010

Webcast - recorded

 
PCI Express 3.0 Compliance - Successfully Navigating the Standard Webcast 
Original broadcast May 7, 2013

Webcast - recorded

 
Oscilloscope Measurements Webcast Series 
Live and on-demand broadcasts that will teach you how to make precise measurements with its Infiniium line of real-time and sampling oscilloscopes.

Webcast