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Phase-Locked Loops (PLL)

Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.

After your design is complete, Agilent's test and measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.

The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution. 

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A Practical Approach to Verifying RFICs with Fast Mismatch Analysis 
Originally broadcast October 28, 2010

Webcast - recorded

 
Ethernet Compliance Testing: Become More Green and Energy Efficient Webcast 
Original broadcast March 20, 2013

Webcast - recorded

 
Genesys Webcasts - "How-To-Design" series  
Originally broadcast in 2009. Access the 6 WebEX recordings

Webcast - recorded

 
PCI Express(R) 3.0 Strategies for Transmitter and Receiver Validation 
Originally broadcast Feb 10, 2011

Webcast - recorded

 
Successful Modulation Analysis in 3 Steps Webcast 
Original broadcast January 22, 2014

Webcast - recorded

 
SuperSpeed USB 3.0 Validation and Compliance Testing Challenges 
Originally broadcast May 18, 2011;

Webcast - recorded

 
USB 3.0 Physical Layer Test Challenges: Gen3 and Beyond Webcast 
Original broadcast June 13, 2013

Webcast - recorded