鎖相迴路
安捷倫提供完整的設計及模擬工具，讓您能夠輕鬆設計、合成和模擬鎖相迴路及頻率合成器，確保您可以達成重要效能目標並製造可靠的元件。利用安捷倫的電子設計自動化軟體，例如 ADS、GoldenGate RFIC模擬器或 Genesys，您可偵測安定時間和相位雜訊等重要特性，並將其最佳化，以獲致優異效能。
完成設計後，則可利用安捷倫的信號源分析儀、示波器及頻譜分析儀等量測儀器，快速量測並驗證您的設計原形與產品。
Agilent E5052B SSA信號源分析儀可針對PLL/VCO設計與製造，執行快速而準確的量測，並可在更短時間內，將高品質、高獲利產品推出上市。無論您是需要量測相位雜訊、調幅雜訊、鎖定時間、VCO調諧效能、諧波雜訊或是直流雜訊，安捷倫EDA軟體讓您一次搞定所有問題。
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ADS Videos on YouTube
Advanced Design System (ADS) Video Library playlist in Agilent EEsof EDA's Channel on YouTube
基本展示 2012-01-27 |
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Agilent EEsof EDA Premier Communications Design Software
Agilent EEsof EDA premier communications design software product overview brochure.
型錄 2011-08-03 |
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1.92 MB
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Discovering Genesys
A collection of Agilent EEsof EDA Genesys video demonstrations and tutorials
基本展示 2011-05-05 |
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What is ADS able to simulate concerning PLLs? (login required)
This page covers simulating phase-locked loops using Advanced Design System (ADS).
應用手冊 2011-03-15 |
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ADS 2011 Videos Debut on YouTube
A collection of Advanced Design System 2011 video demonstrations and tutorials
基本展示 2011-02-25 |
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Discovering ADS
A collection of Agilent EEsof EDA ADS video demonstrations and tutorials
基本展示 2009-06-26 |
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Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluation
This application note describes introduces practical solutions for VCO/PLL performance evaluation and gives actual examples of parameter measurements using the E5052B.
應用手冊 2008-11-21 |
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Characterizing phase-locked-loop signal transition behaviors of Microphonic/Phase-hit
This paper discusses how Agilent's Signal Source Analyzer helps you to identify unwanted phase-locked-loop transition "phase-hits", and achieve easy, comprehensive and accurate phase-locked-loop characterization in both linear and nonlinear regions.
應用手冊 2008-10-02 |
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E5052B Signal Source Analyzer Brochure
This 16-page brochure describes the features and benefits of the E5052B (10 MHz to 7 GHz, 26.5 GHz, or 110 GHz) Signal Source Analyzer.
型錄 2007-04-19 |
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2.38 MB
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Agilent EEsof EDA Customer Support Brochure
型錄 2005-02-01 |
PDF
397 KB
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An Integrated EDA-tools Flow Improves Designers' Productivity
This Article written by Andy Howard (Agilent Technologies) explains application of an integrated front-to-back design flow to improve the quality and efficiency in the design of a prescaler.
專文 2002-05-30 |
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225 KB
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Design and Measurement of a 400 MHz Frequency Synthesizer: Accuracy Proof
This Application Note explains the 400 MHz PLL design with examples and hence giving the engineer a powerful effective tool for designing real PLLs.
應用手冊 2001-11-01 |
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PLL FM-Modulator Suitable for Mobile and Radio Communication Simulation
This Technical Overview details a new PLL-FM Modulator with rapid acquisition time about 1000 times less than the conventional PLL with less spurs which is suitable in mobile and radio communications.
技術總覽 2001-10-31 |
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173 KB
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PLL’s using a Charge Pump, High Divide-by-N Factors, and Decimation before Plotting
This Application Note shows an approach for designing a phase locked loop (PLL) that uses a charge pump, High Divide-by-N Factors, and Decimation before Plotting.
應用手冊 2001-03-20 |
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Optimizing VCO/PLL evaluations and PLL synthesizer designs AN 1330-1
This application note clarifies the role and performance requirements of the synthesized oscillator used in wireless communication equipment, and introduces our test solution for VCO/PLL evaluation.
應用手冊 2000-09-01 |
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1.04 MB
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Simplified Analysis of Phase-Locked Loop Capture and Tracking Range (AN 1200-7)
The Agilent 53310A's ability to measure and display a signal's continuous frequency over time makes dynamic frequency analysis of PLLs easy. A direct measure of the PLL's capture and tracking range is obtained by monitoring the output frequency while the PLL is forced to go in and out of lock. A...
應用手冊 2000-08-01 |
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DesignGuides: Expert Help in the Time-to-Market Race
Agilent EEsof EDA DesignGuides data sheet
產品型錄 1999-07-01 |
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1.91 MB
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Designing to Digital Wireless Specifications using Circuit Envelope Simulation
This Paper by How-Siang Yap discusses the Circuit Envelope technology developed specifically to simulate modern wireless circuits with complex digitally modulated RF signals such as CDMA and TDMA.
技術總覽 1998-06-01 |
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245 KB
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The RC Charge Pump: A Versatile RF Library circuit for PLL’s and Beyond
This Application Note describes the RC Charge Pump; a Versatile RF Library circuit for Phase Locked Loops (PLL’s). Logic gate delays and a diode amplitude demodulator are also possible with this charge-pump.
應用手冊 1998-03-19 |
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941 KB
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Analyzing Phase-Locked Loop Capture and Tracking Range (AN 358-13)
This Application Note is for information only. Agilent no longer sells or supports these products.
應用手冊 1990-10-01 |
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667 KB
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Analyzing Phase-Locked Loop Transients in the Modulation Domain (AN 358-7)
This Application Note is for information only. Agilent no longer sells or supports these products.
應用手冊 1989-10-01 |
PDF
658 KB
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