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Design and Simulation of High-Speed Digital
Agilent tools provide views into the time and frequency domains, revealing the underlying problems and ensuring compliant designs. With Agilent, you'll achieve your best design.
High Speed Digital Design Challenges
- Analyzing complete chip-to-chip links by co-simulating individual components, each at its most appropriate level of abstraction: channel-, circuit- or physical-level
- Importing backplane S-parameter models accurately into circuit and channel simulations, avoiding causality and passivity issues
- Correlating measured and simulated data before using simulation to interpolate between measurement planes and extrapolating to virtual prototypes
What's New
- Agilent Introduces Electrical Retimer Solution to Solve Challenges in Designing Chip-to-Chip Links
- Agilent Technologies Announces High-Speed Digital Seminar Tour with Micron
- ClioSoft Announces the Integration of SOS Design Data Management with Advanced Design System
- Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
- Agilent Technologies to Demonstrate Newest High-Speed Digital Design and Test Solutions at DesignCon
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By Type of Content
- Seminar Materials (7)
- Training Materials (1)
- Tradeshow (2)
- Seminar (2)
- Webcast - recorded (13)
- Webcast (1)
Nach Produkt Kategorie
1-25 of 26
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Agilent Veranstaltungs-Webseite für Deutschland
Willkommen zur neuen Agilent Veranstaltungs-Webseite für Deutschland
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ADMF: Facing the challenges of Super speed USB 3.0 Product Development
Agilent Digital Measurement Forum (ADMF): Facing the challenges of Super speed USB Product Development
Seminar Materials 2008-11-12 |
PDF
1.78 MB
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Astonishing Enhancements to Signal Integrity EDA Tools Using Video Game 3D Glasses and GPUs
Originally broadcast Jan 21, 2010
Webcast - recorded |
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Design and Test Challenges in Next Generation High-Speed Serial Standards
Attend this FREE education workshop at DesignCon 2012, brought to you by Agilent Technologies, Official Host Sponsor of the conference.
Training Materials 2011-11-29 |
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Digital and Photonics Webcast Series
Originally broadcast 2010, 2011. Access the recordings of many broadcasts
Webcast - recorded |
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Digital Webcast Series - Master the high-speed digital test challenge
multiple broadcasts - refer to www.agilent.com/find/DPTwebcasts for the complete list
Webcast - recorded |
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Ethernet Compliance Testing: Become More Green and Energy Efficient Webcast
Original broadcast March 20, 2013
Webcast - recorded |
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Genesys Webcasts - "How-To-Design" series
Originally broadcast in 2009. Access the 6 WebEX recordings
Webcast - recorded |
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High-Sensitivity Current Measurements using an Oscilloscope Webcast
Original broadcast April 17, 2013
Webcast - recorded |
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IMS 2011 (IEEE MTT-S) – Connect, Expert to Expert, at Agilent Avenue
2011 show, last June, 2011; Baltimore Convention Center
Tradeshow |
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IMS 2012 (IEEE MTT-S) – Connect, Expert to Expert, at Agilent Avenue
June 17-22, 2012 in Montréal, Canada
Tradeshow |
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Innovations in EDA: Multi-Technology RF Design Using the New Advances in ADS 2011
Originally broadcast March 1, 2011
Webcast - recorded |
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Innovations in EM Simulation for High Speed Digital Design
Originally broadcast Nov 18, 2010; Part of the Series: Signal Integrity for High Speed Digital Interconnects.
Webcast - recorded |
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Introduction to EMI/EMC Challenges and Their Solution
Agilent EEsof EDA presentation on how to, "Overcome High Speed Digital Design Challenges".
Seminar Materials 2012-02-16 |
PDF
3.46 MB
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Is Simulation a Requirement for Memory Designs Webcast
Live broadcast February 20, 2013; 10am Pacific / 1pm Eastern
Webcast |
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Modeling Optical Fiber Communication with Channel Simulation Webcast
Live broadcast March 6, 2013; 10am Pacific / 1pm Eastern
Webcast - recorded |
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Overcome PI Challenges on Perforated Power/Groung Planes
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.
Seminar Materials 2012-01-19 |
PDF
2.30 MB
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Overcome Signal Integrity Challenges in the multigigabit(s) Era
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.
Seminar Materials 2011-12-15 |
PDF
781 KB
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Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages
A day in the life of a Memory Architect.
Seminar Materials 2011-10-24 |
PDF
1.86 MB
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Signal Integrity Design Using Channel Simulation and EM Co-design
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables
Seminar Materials 2010-04-21 |
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Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.
Webcast - recorded |
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Successful High Speed Digital Design with ADS, EMPro, and SystemVue
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.
Seminar Materials 2011-09-29 |
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Test & Measurement events in Europe, Middle East & Africa
Test & Measurement events in Europe, the Middle East, and Africa - seminars, trade shows, user group meetings, webcasts, tutorials and conferences.
Seminar |
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Understanding Cross Modulation Effects in a Full Duplex LTE Transceiver
Originally broadcast July 22, 2010
Webcast - recorded |
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Using IBIS AMI Models as ‘Executable Data sheets’ in High Speed Digital Interconnect Simulations
Originally broadcast Sept 9, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.
Webcast - recorded |
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