Design and Simulation of High-Speed Digital
Agilent tools provide views into the time and frequency domains, revealing the underlying problems and ensuring compliant designs. With Agilent, you'll achieve your best design.
High Speed Digital Design Challenges
- Analyzing complete chip-to-chip links by co-simulating individual components, each at its most appropriate level of abstraction: channel-, circuit- or physical-level
- Importing backplane S-parameter models accurately into circuit and channel simulations, avoiding causality and passivity issues
- Correlating measured and simulated data before using simulation to interpolate between measurement planes and extrapolating to virtual prototypes
What's New
- ClioSoft Announces the Integration of SOS Design Data Management with Advanced Design System
- Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
- Agilent Technologies to Demonstrate Newest High-Speed Digital Design and Test Solutions at DesignCon
- Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links
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Agilent EEsof EDA Newsletter - Product and Application News
Keep tabs on the latest product and application news and review the archives of the Agilent EEsof EDA Newsletter.
Newsletter 2013-05-14 |
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Follow Agilent EEsof EDA on Twitter!
Twitter enables you to keep current on news and updates with Agilent EEsof through the exchange of quick, frequent answers to one simple question: What are you doing?
Newsletter 2010-03-04 |
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Inphi Delivers Memory Interface Chip for DDR3-1600 Using Advanced Design System
This Success Story details how Inphi delivered memory interface chip for DDR3-1600 using Agilent’s Advance Design System (ADS).
Case Study 2009-03-12 |
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Partner article using ADS: Practical Fiber Weave Effect Modeling -- Lamsim Enterprises, Inc.
Partner article using ADS: Practical Fiber Weave Effect Modeling -- Lamsim Enterprises, Inc.
Article 2011-01-11 |
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Practical Analysis of Backplane Vias - White Paper
This paper describes the methodology of using measurements on a test vehicle to build a high bandwidth, scalable model of long vias which includes the through and stub effects which can be used for system simulation.
Case Study 2009-04-20 |
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S-parameters Without Tears
This article explains s-parameter theory and shows how to create accurate, delay-causal, and passive time-domain models by combining band-limited s-parameter data with knowledge about the physical characteristics of a component.
Journal 2010-01-25 |
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Signal Integrity Analysis and Simulation Tools include IBIS Models
This Article describes the types of models that need to be taken together for high-speed signal integrity analysis, and illustrates their use in a simulation of a high-speed memory circuit.
Article 2004-09-01 |
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Signal Integrity Simulation of PCI Express Gen 2 Channel
Article reprint from XrossTalk Magazine, Janurary 2009, author Jason Boh.
Article 2009-03-23 |
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