Design and Simulation of High-Speed Digital
Agilent tools provide views into the time and frequency domains, revealing the underlying problems and ensuring compliant designs. With Agilent, you'll achieve your best design.
High Speed Digital Design Challenges
- Analyzing complete chip-to-chip links by co-simulating individual components, each at its most appropriate level of abstraction: channel-, circuit- or physical-level
- Importing backplane S-parameter models accurately into circuit and channel simulations, avoiding causality and passivity issues
- Correlating measured and simulated data before using simulation to interpolate between measurement planes and extrapolating to virtual prototypes
새로운 소식
- ClioSoft Announces the Integration of SOS Design Data Management with Advanced Design System
- Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
- Agilent Technologies to Demonstrate Newest High-Speed Digital Design and Test Solutions at DesignCon
- Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links
상세분류 제거1-25 / 26
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S-파라미터 시리즈: 가상 프로빙에 디임베딩 툴 사용 어플리케이션 노트(영문)
까다로운 측정 포인트에 대한 가상 액세스를 위해 디임베딩 툴을 사용하는 방법에 대해 설명합니다.
어플리케이션 노트 2012-03-11 |
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8 Hints for Debugging and Validating High-speed Buses
8 Hints for Debugging High-speed Buses
어플리케이션 노트 2002-03-05 |
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2.24 MB
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DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
어플리케이션 노트 2013-01-24 |
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1.65 MB
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Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
어플리케이션 노트 2001-12-20 |
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1.51 MB
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Designing High Speed Backplanes Utilizing Physical Layer Test System
This Application Note focuses on the problems introduced into the backplane assembly design by the many linear passive components that create reflections due to impedance discontinuities.
어플리케이션 노트 2006-01-18 |
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Effective Reflection Characterization for Active Devices Using ENA Option TDR Application Note
This application note describes Hot TDR measurement, which is an effective characterization method for the reflection of transmitter and receiver.
어플리케이션 노트 2012-01-12 |
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Explore the SERDES Design Space Using the IBIS AMI Channel Simulation Flow
Simulation of modern chip-to-chip links requires you abandon the SPICE-based approach and adopt a new approach based on an IBIS AMI channel simulation flow.
어플리케이션 노트 2012-09-21 |
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Frequency Domain Analysis of Jitter Amplification in Clock Channels
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained.
어플리케이션 노트 2012-11-01 |
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257 KB
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High-Speed Source Synchronous Interface Design
presents considerations for high-speed interface design using examples from a DDRSDRAM implementation.
어플리케이션 노트 2001-08-02 |
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Jitter Analysis Techniques for High Data Rates (AN 1432)
This new application note describes the basic jitter measurements and the specific measurement techniques used in SONet/SDH/OTN and Gigabit Ethernet applications.
어플리케이션 노트 2003-02-03 |
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Limitations and Accuracies of Time and Frequency Domain Analysis of Physical Layer Devices
어플리케이션 노트 2005-11-01 |
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2.83 MB
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Measuring Jitter in Digital Systems (AN 1448-1)
Measuring jitter and how to calculate total jitter.
어플리케이션 노트 2008-01-30 |
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1.91 MB
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On-Chip Design Verification with Xilinx FPGAs
Xilinx Virtex-II Pro devices have redefined FPGAs.
어플리케이션 노트 2003-04-30 |
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Power Toolbox for Embedded System Designs
Properly Powering On and Off Multiple Power Inputs in Embedded Designs
어플리케이션 노트 2009-06-01 |
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S-Parameter Techniques for Faster, More Accurate Network Design (AN 95-1)
This Application Note is for information only. Agilent no longer sells or supports these products.
어플리케이션 노트 1967-02-01 |
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3.10 MB
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Signal Integrity Analysis Series Part 1: Single-Port TDR, TDR/TDT, & 2-Port TDR
This Application Note focuses on part 1: those which use a single-port TDR, those which use TDR/TDT, and those which use 2-port TDR.
어플리케이션 노트 2007-01-01 |
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3.50 MB
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Signal Integrity Analysis Series Part 2: 4-Port TDR/VNA/PLTS
This Application Note focuses on part 2: those which use a 4-port TDR/VNA/PLTS.
어플리케이션 노트 2007-02-21 |
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2.75 MB
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Signal Integrity Analysis Series Part 3: The ABCs of De-Embedding
This Application Note focuses on Part 3: The ABCs of De-Embedding explaining different de-embedding techniques & shows how to minimize fixture effects for best results.
어플리케이션 노트 2007-07-01 |
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2.44 MB
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Simulating FPGA Power Integrity Using S-Parameter Models
This application note describes how self-impedance (frequency) can easily be determined by simulating the frequency domain self-impedance profile of a Power Distribution Network (PDN).
어플리케이션 노트 2012-04-02 |
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5.68 MB
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Simulating High-Speed Serial Channels with IBIS-AMI Models
This paper reviews some of the benefits and limitations of using IBIS models and introduces the new AMI extensions to the latest IBIS version 5.0 specification.
어플리케이션 노트 2011-11-15 |
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Spectrum Analysis Application Notes
Download a copy of AN150, both high and low resolution PDF's are available.
어플리케이션 노트 2004-04-27 |
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Understanding Signal Integrity
This is a technical note that was featured in the AMS Newsletter, Volume 1, Issue 2. This technical note discusses the problems that engineers have with signal integrity and solutions to help address the problems.
어플리케이션 노트 2002-04-18 |
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287 KB
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Understanding the Kramers-Kronig Relation Using A Pictorial Proof
The Kramers-Kronig relation lets us build a causal time-domain model from bandlimited s-parameters. This pictorial proof aids understanding of the physics of causality and hence the validity of this approach.
어플리케이션 노트 2010-03-31 |
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Using ADS for Signal Integrity Optimization
This white paper shows how to replace a multi-dimensional sweep of a long running PRBS time-domain simulation (including manual data evaluation) by short, channel-pulse characterization in the Advanced Design System to efficiently optimize a channel.
어플리케이션 노트 2009-10-19 |
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Using Clock Jitter Analysis to Reduce BER in Serial Data Applications
This Application Note emphasizes on the emerging techniques for reference clock jitter analysis from the perspective of oscillator physics, phase noise theory, and serial data technology.
어플리케이션 노트 2006-12-01 |
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1.15 MB
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