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Boundary Scan

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Modifying DDR Libraries for Silicon Nail Test Generation on the Agilent x1149 Boundary Scan Analyzer 
This application note describes how to modify DDR libraries to generate silicon nails tests on the Agilent x1149 Boundary Scan Analyzer.

應用手冊 2013-11-07

PDF PDF 382 KB
Releasing the “Test Sequence” and “Test” to Production on the Agilent x1149 Boundary Scan Analyzer 
This application note describes how to release test sequences and tests to production when using the Agilent x1149 Boundary Scan Analyzer.

應用手冊 2013-10-18

PDF PDF 523 KB
Testing DDR Memory; How On-Chip DFT Helps 
This paper discusses DDR memory testing challenges we see today, and how the adoption of DFT capabilities pays off in higher test coverage, better diagnostics and reduced programming/support time.

專文 2012-04-17

PDF PDF 530 KB
Boundary-Scan Advanced Diagnostic Methods 
This paper illustrates how usage of boundary scan circuit information and predictive analysis of potential assembly faults will provide more precise and accurate diagnostic information.

專文 2012-04-17

PDF PDF 1.20 MB
How to build a fixture for use with the Agilent Cover-Extend Technology 
Cover-Extend Technology is Agilent’s latest limited access solution for in-circuit test. This paper documents the necessary information for a fixture vendor to build a Cover-Extend fixture.

應用手冊 2011-06-24

PDF PDF 1.09 MB
Solutions for Undetected Shorts on IEEE 1149.1 Self-Monitoring Pins 
This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins, and potential mitigating solutions.

專文 2010-12-10

PDF PDF 789 KB
Principal Component Analysis-Based Compensation for Measurement Errors 
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE

專文 2010-12-10

PDF PDF 1.10 MB
Surviving State Disruptions Caused by Test: the "Lobotomy Problem" 
This paper examines some issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing. Published with kind permission of the IEEE

專文 2010-12-10

PDF PDF 402 KB
Agilent Silicon Nail 可擴大測試範圍 

基本展示 2010-10-28

 
Limited Access Tools Improve Test Coverage 
Smaller test pads and shrinking board sizes are posing new challenges, and driving innovations to overcome limited access with new test solutions. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend

專文 2010-10-20

PDF PDF 275 KB
The Proposed IEEE Test Standards 
There is a resurgence of interest in Boundary Scan and Built in Self Test (BIST) initiatives to be part of IEEE standards. This article explains the IEEE standard and their benefits to the industry. Agilent Boundary Scan, 1149.6, 1149.1, bead probes, cover-extend

專文 2010-10-20

PDF PDF 2.83 MB
Boundary Scan Press Releases 

新聞資料 2010-07-14

 
Comparing Boundary Scan Methods White Paper 
The need for reusable tests is driving standalone boundary scan-ICT integration. This article first appeared in the September 2009 issue of Circuits Assembly and is reprinted with kind permission.

專文 2010-06-09

PDF PDF 2.68 MB
Medalist VTEP v2.0 Powered, with Cover-Extend technology  
This brochure provides an overview of Cover-Extend under the VTEP v2.0 Powered vectorless test suite

型錄 2010-04-06

PDF PDF 237 KB
Medalist i3070 In Circuit Test – Utilizing the most comprehensive Limited Access 
This article introduces the seven most prominent and effective limited access tools on the Agilent Medalist i3070 ICT, collectively known Super 7 suite.

應用手冊 2009-03-06

PDF PDF 342 KB