Phase-Locked Loops (PLL)

PLL design, synthesis, optimization and test

Specifications

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		Titre/description	Date	Type
	PDF 1.91 MB	DesignGuides: Expert Help in the Time-to-Market Race Agilent EEsof EDA DesignGuides data sheet	1999-07-01	Data Sheet
	PDF 245 KB	Designing to Digital Wireless Specifications using Circuit Envelope Simulation This Paper by How-Siang Yap discusses the Circuit Envelope technology developed specifically to simulate modern wireless circuits with complex digitally modulated RF signals such as CDMA and TDMA.	1998-06-01	Technical Overview

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