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Digital Design & Interconnect Standards

Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.

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10 Reasons to Upgrade to a 16800 or 16900 Series Logic Analyzer 
10 Reasons to Upgrade to a 16800 or 16900 Series Logic Analyzer

Application Note 2007-12-03

PDF PDF 999 KB
Languages 
6 Hints for Better SATA and SAS Measurements 
These 6 Hints for better SATA and SAS measurements cover Tx, Rx, Impedance and Return Loss, and Host/Device Digital testing challenges.

Application Note 2012-02-02

PDF PDF 1.59 MB
A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses 
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.

Application Note 2008-09-10

PDF PDF 792 KB
Languages 
Agilent Method of Implementation (MOI) for DisplayPort Cable-Connector Assembly Compliance Test 
Agilent Method of Implementation (MOI) for DisplayPort Cable-Connector Assembly Compliance Test Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2013-02-18

PDF PDF 1.29 MB
Agilent Method of Implementation (MOI) for MHL Cables Compliance Tests 
Agilent Method of Implementation (MOI) for MHL Cable Compliance Tests Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2013-02-14

PDF PDF 1.76 MB
Languages 
Agilent Method of Implementation (MOI) for MIPI D-PHY Conformance Tests 
Agilent Method of Implementation (MOI) for MIPI D-PHY Conformance Tests Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2011-12-01

PDF PDF 920 KB
Agilent Method of Implementation (MOI) for MIPI M-PHY Conformance Tests 
Agilent Method of Implementation (MOI) for MIPI M-PHY Conformance Tests Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2011-12-01

PDF PDF 918 KB
Agilent Method of Implementation (MOI) for PCI Express 3.0 PCB Differential Trace Impedance Test 
Agilent Method of Implementation (MOI) for PCI Express 3.0 PCB Differential Trace Impedance Test Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2012-10-16

PDF PDF 1.62 MB
Agilent Method of Implementation (MOI) for SATA RXTX Compliance Test 
Agilent Method of Implementation (MOI) for SATA RXTX Compliance Test Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2011-01-12

PDF PDF 1.19 MB
Agilent Method of Implementation (MOI) for SATA SI Compliance Test 
Agilent Method of Implementation (MOI) for SATA SI Compliance Test Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2011-01-12

PDF PDF 1.41 MB
Agilent Method of Implementation (MOI) for USB3.0 Cable-Connector Assembly Compliance Test 
Agilent Method of Implementation (MOI) for USB3.0 Cable-Connector Assembly Compliance Test Using Agilent E5071C ENA Network Analyzer Option TDR

Application Note 2012-12-17

PDF PDF 1.82 MB
An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T 
The technology used in these ports, commonly known as “LAN” or “NIC” ports, is usually one of the 10BASE-T, 100BASE-TX, and 1000BASE-T standards or a combination of them.

Application Note 2011-01-11

PDF PDF 1.21 MB
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Comparison of Different Jitter Analysis Techniques With a Precision Transmitter 
This white paper describes how various jitter analysis techniques give dissimilar results. Which is right? We built a precision jitter transmitter to compare results of different techniques where test sets were exposed to known levels of jitter.

Application Note 2006-04-06

PDF PDF 164 KB
Crossing the Digital-Analog Divide - White Paper 
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.

Application Note 2012-05-02

PDF PDF 6.46 MB
Debugging USB 2.0: It's Not Just A Digital World (AN 1382-3) 
Debugging USB 2.0 Systems

Application Note 2006-10-05

PDF PDF 392 KB
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Designing and Validating High-Speed Memory Buses (AN 1382-2) 
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

Application Note 2001-12-20

PDF PDF 1.51 MB
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Designing High Speed Backplanes Utilizing Physical Layer Test System 
This Application Note focuses on the problems introduced into the backplane assembly design by the many linear passive components that create reflections due to impedance discontinuities.

Application Note 2006-01-18

PDF PDF 1.24 MB
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Effective Reflection Characterization for Active Devices Using ENA Option TDR Application Note 
This application note describes Hot TDR measurement, which is an effective characterization method for the reflection of transmitter and receiver.

Application Note 2012-01-12

PDF PDF 416 KB
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Evaluating Oscilloscope Sample Rates vs. Sampling Fidelity 
Evaluating Oscilloscope Sample Rates vs. Sampling Fidelity: How to Make the Most Accurate Digital Measurements When you select an oscilloscope for accurate, high-speed digital measurements, sampling fidelity can often be more important than maximum sample rate.

Application Note 2012-11-11

PDF PDF 1.56 MB
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Explore the SERDES Design Space Using the IBIS AMI Channel Simulation Flow 
Simulation of modern chip-to-chip links requires you abandon the SPICE-based approach and adopt a new approach based on an IBIS AMI channel simulation flow.

Application Note 2012-09-21

PDF PDF 467 KB
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Frequency Domain Analysis of Jitter Amplification in Clock Channels 
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained.

Application Note 2012-11-01

PDF PDF 257 KB
How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY) 
How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY)

Application Note 2007-07-30

PDF PDF 611 KB
Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems 
Application Note 1575

Application Note 2006-04-14

PDF PDF 120 KB
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Improving Usability and Performance in High-Bandwidth Active Oscilloscope Probes (AN 1419-02) 
Understand how to get minimal probe loading and highest-possible-performance representation of your signal.

Application Note 2002-11-01

PDF PDF 912 KB
Languages 
Limitations and Accuracies of Time and Frequency Domain Analysis of Physical Layer Devices 

Application Note 2005-11-01

PDF PDF 2.83 MB
Languages 

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