Digital Design & Interconnect Standards
Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.
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- Application Note (165)
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26-50 of 165
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Agilent N4900 Serial BERT Series Jitter Injection and Analysis Capabilities
The fundamentals of Jitter and it's capabilities with the N4900.
Application Note 2003-11-01 |
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3.99 MB
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An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T
The technology used in these ports, commonly known as “LAN” or “NIC” ports, is usually one of the 10BASE-T, 100BASE-TX, and 1000BASE-T standards or a combination of them.
Application Note 2011-01-11 |
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1.21 MB
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Application Note 1382-4: I/O System and Chip Validation in PCI and PCI-X Systems (AN 1382-4)
Validation of computer systems and subsystems is becoming increasingly complex as input/output (I/O) systems and peripherals become more intelligent. The role of data-transfer is being delegated to the I/O systems instead of the CPU, causing data traffic to move in several directions...
Application Note 2001-12-20 |
PDF
920 KB
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Application Note2: Verify if a device can stand all kinds of protocol variations
Validating servers and workstations that contain various I/O systems, various peripherals and high and low-speed devices, has become a sophisticated task.
If you are a validation engineer, you have to ensure that server products can stand all possible protocol variations; that corner cases...
Application Note 2001-10-04 |
PDF
556 KB
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Application Note4: Read and write register values of your device before a driver is available
The Agilent PCI/PCI-X Exerciser, a combination of testcard and software, simplifies the task of reading values from (peek) and writing values into (poke) registers or memory before a driver is available.
Aims of this Application Note
To show how to access registers of a device before a...
Application Note 2001-10-05 |
PDF
363 KB
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Automated PCI Express Receiver Compliance Test and Characterization with N5990A
This product note shows how to use the test automation software platform to verify and debug your PCI Express bus designs. As an example, a multi-lane add-in card is used.
Application Note 2006-08-29 |
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444 KB
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Automated USB 2.0 Receiver Compliance Test and Characterization with the Agilent N5990A
Automated USB 2.0 Receiver Compliance Test and Characterization with the Agilent N5990A Software Platform: 8 pages
Application Note 2007-01-31 |
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272 KB
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Benefits of using PCI Express 2.0.
An overview of the main features and benefits of using PCI Express 2.0
Application Note 2008-10-17 |
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764 KB
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Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluation
This application note describes introduces practical solutions for VCO/PLL performance evaluation and gives actual examples of parameter measurements using the E5052B.
Application Note 2008-11-21 |
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2.91 MB
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Calibrated Jitter, Jitter Tolerance Test and Jitter Laboratory with the Agilent J-BERT N4903A
This application note describes the N4903A BERT characterization solution for emerging serial gigabit devices: it helps engineers make quick and accurate jitter tolerance tests, which have been complicated and hard to do in the past.
Application Note 2006-07-18 |
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5.33 MB
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Characterization of Balanced Digital Components and Communication Paths
Application Note 2001-11-19 |
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1.01 MB
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Characterizing Clock Jitter through Phase Noise Measurements Speeds up Design Verification Process
This white paper discusses a new measurement method for obtaining highly accurate low random jitter (RJ) measurements and performing real-time analysis of RJ and periodic jitter (PJ) of components.
Application Note 2008-11-20 |
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Characterizing High-Speed Optical Transmitters Compliance Testing with the Agilent 86100A AN: 1340-1
This application note will focus on the testing of opticaltransmitters used by three communications technologies:SONET/SHD, Gigabit Ethernet, and Fibre Channel.
Application Note 2000-08-01 |
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2.01 MB
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Comparison of Different Jitter Analysis Techniques With a Precision Transmitter
This white paper describes how various jitter analysis techniques give dissimilar results. Which is right? We built a precision jitter transmitter to compare results of different techniques where test sets were exposed to known levels of jitter.
Application Note 2006-04-06 |
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164 KB
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Crossing the Digital-Analog Divide - White Paper
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.
Application Note 2012-05-02 |
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6.46 MB
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DDR Memory Overview, Development Cycle, and Challenges - Technical Overview
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.
Application Note 2012-12-14 |
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1.37 MB
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DDR Probing for Physical Layer and Functional Testing
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.
Application Note 2008-12-19 |
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617 KB
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DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
Application Note 2013-01-24 |
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1.65 MB
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Debugging Parallel RapidIO Designs
Application Note 2003-01-09 |
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356 KB
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Debugging Signal Integrity and Protocol Layers on DDR Designs
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.
Application Note 2008-12-19 |
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984 KB
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Debugging USB 2.0: It's Not Just A Digital World (AN 1382-3)
Debugging USB 2.0 Systems
Application Note 2006-10-05 |
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Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
Application Note 2001-12-20 |
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1.51 MB
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Designing High Speed Backplanes Utilizing Physical Layer Test System
This Application Note focuses on the problems introduced into the backplane assembly design by the many linear passive components that create reflections due to impedance discontinuities.
Application Note 2006-01-18 |
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Differential S-parameter Measurements of PCI Express Connectors(AN 1463-3)
Frequency domain differential S-parameter measurements are becoming important for the components used in the latest high-speed digital communication technologies such as Gigabit Ethernet, Infiniband, PCI Express, and so on.
Application Note 2003-07-25 |
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Direct Rambus™ Architecture and Measurements
Includes and overview of Direct Rambus™ channel electrical and logical architecture and Direct RDRAM device physical architecture. Presents measurement examples.
Application Note 2001-07-18 |
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