Digital Design & Interconnect Standards

Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.

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6 Hints for Better SATA and SAS Measurements These 6 Hints for better SATA and SAS measurements cover Tx, Rx, Impedance and Return Loss, and Host/Device Digital testing challenges. Application Note 2012-02-02	PDF 1.59 MB
8 Hints for Debugging and Validating High-speed Buses 8 Hints for Debugging High-speed Buses Application Note 2002-03-05	PDF 2.24 MB
8 Hints for Debugging Siemens MCU-based Designs A new type of instrument, the mixed signal oscilloscope (MSO), closes the gap in MCU debugging tools. The Agilent 54645D from Hewlett-Packard combines two analog scope channels with 16 digital logic channels, so you can monitor analog and digital lines at the same time. This MSO offers more... Application Note 1998-11-01	PDF 736 KB
A Simple, Powerful Method to Characterize Differential Interconnects The Automatic Fixture Removal (AFR) process is a new technique to extract accurate, high bandwidth models of interconnects that is both simple and accurate. Application Note 2011-06-17	PDF 3.48 MB
Advanced Jitter Generation and Analysis Product Note This product note shows how the Agilent pulse generators can be used with the DCA-J Oscilloscope. Application Note 2004-10-04	PDF 549 KB
Advanced Memory Buffer (AMB), Characterization of Timing and Voltage Specification Advanced Memory Buffer (AMB), Characterization of Timing and Voltage Specification Application Note 2005-09-22	PDF 812 KB
Advanced VNA-Based Test Systems for Analysis of High-Speed Digital Interconnect - Application Note Discusses interconnect testing and present solutions based on the latest generation of test software (PLTS2011) for Agilent's line of performance network analyzers (PNAs) focused on Software. Application Note 2012-01-19	PDF 2.22 MB Languages English \| 2012-01-19 \| PDF 2.22 MB 中文（简体） \| 2012-01-19 \| PDF 2.22 MB 한국어 \| 2012-01-19 \| PDF 2.22 MB
Agilent N4900 Serial BERT Series Jitter Injection and Analysis Capabilities The fundamentals of Jitter and it's capabilities with the N4900. Application Note 2003-11-01	PDF 3.99 MB Languages English \| 2003-11-01 \| PDF 3.99 MB 中文（简体） \| 2003-07-17 \| PDF 1.77 MB
Automated PCI Express Receiver Compliance Test and Characterization with N5990A This product note shows how to use the test automation software platform to verify and debug your PCI Express bus designs. As an example, a multi-lane add-in card is used. Application Note 2006-08-29	PDF 444 KB
Automated USB 2.0 Receiver Compliance Test and Characterization with the Agilent N5990A Automated USB 2.0 Receiver Compliance Test and Characterization with the Agilent N5990A Software Platform: 8 pages Application Note 2007-01-31	PDF 272 KB
Calibrated Jitter, Jitter Tolerance Test and Jitter Laboratory with the Agilent J-BERT N4903A This application note describes the N4903A BERT characterization solution for emerging serial gigabit devices: it helps engineers make quick and accurate jitter tolerance tests, which have been complicated and hard to do in the past. Application Note 2006-07-18	PDF 5.33 MB
Characterization of Balanced Digital Components and Communication Paths Application Note 2001-11-19	PDF 1.01 MB
Characterizing Clock Jitter through Phase Noise Measurements Speeds up Design Verification Process This white paper discusses a new measurement method for obtaining highly accurate low random jitter (RJ) measurements and performing real-time analysis of RJ and periodic jitter (PJ) of components. Application Note 2008-11-20	PDF 688 KB Languages English \| 2008-11-20 \| PDF 688 KB 中文（简体） \| 2008-12-01 \| PDF 620 KB 日本語 \| 2009-01-14 \| PDF 1.74 MB
Characterizing High-Speed Optical Transmitters Compliance Testing with the Agilent 86100A AN: 1340-1 This application note will focus on the testing of opticaltransmitters used by three communications technologies:SONET/SHD, Gigabit Ethernet, and Fibre Channel. Application Note 2000-08-01	PDF 2.01 MB Languages English \| 2000-08-01 \| PDF 2.01 MB 中文（简体） \| 2000-08-01 \| PDF 1.96 MB
Comparison of Different Jitter Analysis Techniques With a Precision Transmitter This white paper describes how various jitter analysis techniques give dissimilar results. Which is right? We built a precision jitter transmitter to compare results of different techniques where test sets were exposed to known levels of jitter. Application Note 2006-04-06	PDF 164 KB
Crossing the Digital-Analog Divide - White Paper This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform. Application Note 2012-05-02	PDF 6.46 MB
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates. Application Note 2013-01-24	PDF 1.65 MB
Debugging Parallel RapidIO Designs Application Note 2003-01-09	PDF 356 KB Languages English \| 2003-01-09 \| PDF 356 KB 日本語 \| 2003-04-25 \| PDF 1.41 MB
Debugging Signal Integrity and Protocol Layers on DDR Designs As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures. Application Note 2008-12-19	PDF 984 KB
Debugging USB 2.0: It's Not Just A Digital World (AN 1382-3) Debugging USB 2.0 Systems Application Note 2006-10-05	PDF 392 KB Languages English \| 2006-10-05 \| PDF 392 KB 日本語 \| 2006-04-25 \| PDF 1.12 MB 中文（繁體） \| 2002-12-21 \| PDF 2.60 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2) DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high... Application Note 2001-12-20	PDF 1.51 MB Languages English \| 2001-12-20 \| PDF 1.51 MB 日本語 \| 2002-04-04 \| PDF 633 KB
Designing High Speed Backplanes Utilizing Physical Layer Test System This Application Note focuses on the problems introduced into the backplane assembly design by the many linear passive components that create reflections due to impedance discontinuities. Application Note 2006-01-18	PDF 1.24 MB Languages English \| 2006-01-18 \| PDF 1.24 MB 中文（简体） \| 2006-05-01 \| PDF 3.27 MB 日本語 \| 2006-05-31 \| PDF 1.94 MB
Effective Reflection Characterization for Active Devices Using ENA Option TDR Application Note This application note describes Hot TDR measurement, which is an effective characterization method for the reflection of transmitter and receiver. Application Note 2012-01-12	PDF 416 KB Languages English \| 2012-01-12 \| PDF 416 KB 日本語 \| 2012-02-27 \| PDF 1.45 MB
Ensuring Compliance and Interoperability of DDR Designs The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually. Application Note 2008-12-19	PDF 379 KB
Evaluating Microstrip with Time Domain Reflectometry (AN 1304-1) This application note discusses microstrip transmission line techniques that were evaluated using TDR measurements. Application Note 2000-11-01	PDF 349 KB Languages English \| 2000-11-01 \| PDF 349 KB 日本語 \| 2001-01-31 \| PDF 496 KB

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