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New ADS DDR4 Compliance Test Bench for Solving the Simulation-Measurement Correlation Challenge 
Agilent introduces Advanced Design System DDR4 Compliance Test Bench, which enables a complete workflow for DDR4 engineers from simulation of a candidate design through measurement of the finished prototype. The solution is ideal for semiconductor companies developing DDR controller IP; those developing DRAM chips and DIMMs; and OEMs integrating the controller and DIMM into a system using PCB technology.

プレス資料 2014-06-30

 
Quickly Validate Designs for DOCSIS 3.1 Compliance - Application Brief 
This “DOCSIS 3.1 Test Solution" app brief gives insight into Agilent solutions that can be used for testing DOCSIS 3.1 transmitters, receivers and components.

アプリケーション・ノート 2014-06-24

PDF PDF 746 KB
DDRメモリのデザイン/テストの概要 
DDRデザインは、インターコネクト・デザイン、アクティブ信号検証、プロトコル検証、ファンクション・テストの4つに分割できます

ブローシャ 2014-06-03

PDF PDF 571 KB
Network Analyzer Time Domain Reflectometry (TDR) Measurements – Granite River Labs 
Network Analyzer Time Domain Reflectometry (TDR) Measurements from Granite River Labs and Agilent

ソリューション概要 2014-04-29

 
DisplayPort 1.2 Link Layer Testing - FuturePlus 
DisplayPort 1.2 Link Layer Testing Solution from FuturePlus and Agilent.

ソリューション概要 2014-04-29

 
DDR4 Protocol Analysis - FuturePlus 
DDR4 Protocol Analysis from FuturePlus and Agilent.

ソリューション概要 2014-04-29

 
Agilent Method of Implementation (MOI) for 10GBASE-KR/40GBASE-KR4 Ethernet Interconnect Tests 
Agilent Method of Implementation (MOI) for 10GBASE-KR/40GBASE-KR4 Ethernet Interconnect Tests Using Agilent E5071C ENA Option TDR

アプリケーション・ノート 2014-04-21

PDF PDF 1.71 MB
Agilent Method of Implementation (MOI) for 10GBASE-KR/40GBASE-KR4 Ethernet Tx/Rx Return Loss Tests 
Agilent Method of Implementation (MOI) for 10GBASE-KR/40GBASE-KR4 Ethernet Tx/Rx Return Loss Tests Using Agilent E5071C ENA Option TDR

アプリケーション・ノート 2014-04-21

PDF PDF 1.03 MB
10GBASE-KR/40GBASE-KR4 Interconnect & Tx/Rx Tests - Test Solution Overview Using the ENA Option TDR 
This describes how to make measurements of 10GBASE-KR/40GBASE-KR4 Ethernet Interconnect & Transmitter/Receiver (Tx/Rx) Tests by using the Agilent E5071C ENA Option TDR.

技術概要 2014-04-21

PDF PDF 3.54 MB
Agilent's Certification of HDMI 2.0 Test Solution 
Agilent Technologies Announces Certification of HDMI 2.0 Test Solution for HDMI 2.0 Compliance Test, With Widest Coverage of Test Items

プレス資料 2014-04-17

 
Oscilloscope Probe Switching - BitifEye 
Oscilloscope Probe Switching Solution from BitifEye and Agilent.

ソリューション概要 2014-04-09

 
HDMI Cable Testing - BitifEye 
HDMI Cable Testing Solution from BitifEye and Agilent.

ソリューション概要 2014-04-09

 
USB 3.0 Cable Testing - BitifEye 
USB 3.0 Cable Testing Solution from BitifEye and Agilent.

ソリューション概要 2014-04-09

 
MIPI™ Phy S-Param & Impedance Conformance Test - Test Solution Overview Using the ENA Option TDR 

技術概要 2014-04-08

PDF PDF 2.92 MB
Method of Implementation(MOI) for MIPI M-PHY Interface S-Parameter and Impedance Conformance Tests 
Agilent Method of Implementation (MOI) for MIPI M-PHY Interface S-Parameter and Impedance Conformance Tests Using Agilent E5071C ENA Network Analyzer Option TDR

アプリケーション・ノート 2014-03-20

PDF PDF 978 KB
ADS Videos on YouTube 
Advanced Design System (ADS) Video Library playlist in Agilent EEsof EDA's Channel on YouTube

デモ 2014-03-20

 
Discovering ADS 
A collection of Agilent EEsof EDA ADS video demonstrations and tutorials

デモ 2014-03-20

 
Digital Design & Interconnect Standards - Brochure 
Brochure shows Agilent’s high-speed digital solution set , a range of essential tools, measurement and simulation—that will help cut through the challenges of gigabit digital designs.

ブローシャ 2014-02-20

PDF PDF 6.47 MB
ADS 2014 Dramatically Improves Design Productivity and Efficiency 
Agilent announces a powerful new version of Advanced Design System software, ADS 2014. Designed to dramatically improve design productivity and efficiency with new technologies and capabilities, ADS 2014 is the software's most significant ADS release to date.

プレス資料 2014-02-20

 
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

記事 2014-02-18

PDF PDF 2.99 MB
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies 
This paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

記事 2014-02-18

PDF PDF 3.28 MB
Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver 
This paper shows the right combination of measurement and simulation techniques, and how the previously existing barriers for using de-embedding have been eliminated.

記事 2014-02-18

PDF PDF 3.82 MB
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 
This paper presents a methodology to setup and analyze Simultaneous Switching Noise for DDR4 applications using Touchstone v2.0 models.

記事 2014-02-18

PDF PDF 8.07 MB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links 
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

記事 2014-02-18

PDF PDF 1.78 MB
Mechanism of Jitter Amplification in Clock Channels 
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

記事 2014-02-18

PDF PDF 671 KB

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