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Digital Design & Interconnect Standards

Achieve your best design with Agilent. Investigate specific solutions for high speed standards plus solutions for your high-speed digital design cycle (design, simulation, analysis, debug compliance and signal integrity) challenges.

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Analyzing Digital Jitter and its Component eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 35 KB
Building a Precision Jitter Source 
Presentation, June 1, 2004 From the Japan Agilent Digital Measurement Forum, this presentation reviews the construction of a precision jitter source for analyzing digital jitter measurements.

Seminar Materials 2004-06-01

PDF PDF 623 KB
Characterization and Modeling of a High Speed Backplane Differential Channels eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 80 KB
Hacking the Backplane:Complete Differential Channel Characterization & Analysis from 4-port Meas. 

Seminar Materials 2008-11-09

 
Introduction to EMI/EMC Challenges and Their Solution 
Agilent EEsof EDA presentation on how to, "Overcome High Speed Digital Design Challenges".

Seminar Materials 2012-02-16

PDF PDF 3.46 MB
Jitter Analysis: What Works, What Doesn't & Why eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 63 KB
Jitter in Digital Circuits eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 34 KB
Jitter Measurements for High-Speed Digital 
Jitter Measurements for High-Speed Digital Transmission

Seminar Materials 2006-06-14

PDF PDF 44 KB
Jitter Measurements with a High-Speed Scope eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 117 KB
Minimizing Crosstalk in Hi-Speed Interconnects using Measurement-based Modeling 
This Presentation presented by Mike Resso (Agilent Technologies) focuses on minimizing crosstalk in high speed interconnects using measurement-based modeling.

Seminar Materials 2006-09-01

PDF PDF 1.50 MB
Overcome PI Challenges on Perforated Power/Groung Planes 
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.

Seminar Materials 2012-01-19

PDF PDF 2.30 MB
Overcome Signal Integrity Challenges in the multigigabit(s) Era 
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.

Seminar Materials 2011-12-15

PDF PDF 781 KB
Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages 
A day in the life of a Memory Architect.

Seminar Materials 2011-10-24

PDF PDF 1.86 MB
Signal Integrity Design Using Channel Simulation and EM Co-design 
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables

Seminar Materials 2010-04-21

 
Signal Integrity eSeminar Series Q&A: Being Successful with Fully Buffered DIMM (FBD) Designs 
The following Questions and Answers were created from the live eSeminar broadcast of January 25, 2005. You can view the archived eSeminar by going to

Seminar Materials 2005-01-25

PDF PDF 60 KB
Solving Real World Jitter Problems for High-Speed Communications eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 53 KB
Successful High Speed Digital Design with ADS, EMPro, and SystemVue 
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.

Seminar Materials 2011-09-29

 
TDR vs. VNA Interconnect Characterization eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 18 KB
Testing Receiver Jitter Tolerance eSeminar FAQs 
Testing Receiver Jitter Tolerance eSeminar FAQs

Seminar Materials 2006-06-14

PDF PDF 50 KB
Why Do Measurement-based Channel Modeling? 
Adobe .pdf of the paper presented at the High-Speed Digital Seminar, Ensuring MultiGigabit Design Success

Seminar Materials 2008-01-20

PDF PDF 3.62 MB