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Digital Design & Interconnect Standards

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In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Agilent’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Agilent - achieve your best design

Achieve signal integrity in high-speed design with these useful tools, demos, videos and more 
 

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Successful High-Speed Digital Design for PC board using ADS 
A hands-on workshop on how to solve increasingly difficult signal integrity and power integrity challenges using Advanced Design System.

Seminar Materials 2014-02-27

 
High-Speed Digital Design & Verification Seminar 
A methodology for predictable design closure in the high speed digital era.

Seminar Materials 2013-11-22

PDF PDF 5.45 MB
How to Characterize and Debug High-Speed Digital Links on Your Physical Prototype 
What part of your design is eating up your Eye margins?

Seminar Materials 2013-11-22

PDF PDF 3.70 MB
How to Anticipate Signal Integrity Issues 
Improve channel simulation by using an electromagnetic based model

Seminar Materials 2013-11-22

PDF PDF 9.21 MB
Solving New High-Speed Design Challenges with ADS 2013.06 
In this seminar, leading Agilent EEsof R&D Designers provide a first-hand look at the new HSD features for the world class ADS transient and channel convolution simulators.

Seminar Materials 2013-07-10

 
Introduction to EMI/EMC Challenges and Their Solution 
Agilent EEsof EDA presentation on how to, "Overcome High Speed Digital Design Challenges".

Seminar Materials 2012-02-16

PDF PDF 3.46 MB
Overcome PI Challenges on Perforated Power/Groung Planes 
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.

Seminar Materials 2012-01-19

PDF PDF 2.30 MB
Overcome Signal Integrity Challenges in the multigigabit(s) Era 
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.

Seminar Materials 2011-12-15

PDF PDF 781 KB
Design and Test Challenges in Next Generation High-Speed Serial Standards 
Attend this FREE education workshop at DesignCon 2012, brought to you by Agilent Technologies, Official Host Sponsor of the conference.

Training Materials 2011-11-29

 
View the recorded webcast - How to handle USB 3.0 physical layer test requirements 
How to handle USB 3.0 physical layer test requirements.

Training Materials 2011-11-08

 
View the recorded webcast - Be ready for the next generation HDMI standard 
Be ready for the next generation HDMI standard

Training Materials 2011-11-08

 
View the recorded webcast - Introduction to MIPI device test 
Introduction to MIPI device test

Training Materials 2011-11-08

 
Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages 
A day in the life of a Memory Architect.

Seminar Materials 2011-10-24

PDF PDF 1.86 MB
Enabling MIPI Physical Layer Test- High Speed and Characterization 

Seminar Materials 2011-10-04

 
Successful High Speed Digital Design with ADS, EMPro, and SystemVue 
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.

Seminar Materials 2011-09-29

 
Signal Integrity Design Using Channel Simulation and EM Co-design 
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables

Seminar Materials 2010-04-21

 
Tips to Debugging DDR 1, 2 and 3 Physical and Protocol Layer Issues webcast 

Training Materials 2009-01-06

 
ADMF: Facing the challenges of Super speed USB 3.0 Product Development  
Agilent Digital Measurement Forum (ADMF): Facing the challenges of Super speed USB Product Development

Seminar Materials 2008-11-12

PDF PDF 1.78 MB
Hacking the Backplane:Complete Differential Channel Characterization & Analysis from 4-port Meas. 

Seminar Materials 2008-11-09

 
How to Solve DDR Signal Integrity Validation Challenges 
How to Solve DDR Signal Integrity Validation Challenges

Training Materials 2008-02-13

 
Why Do Measurement-based Channel Modeling? 
Adobe .pdf of the paper presented at the High-Speed Digital Seminar, Ensuring MultiGigabit Design Success

Seminar Materials 2008-01-20

PDF PDF 3.62 MB
Minimizing Crosstalk in Hi-Speed Interconnects using Measurement-based Modeling 
This Presentation presented by Mike Resso (Agilent Technologies) focuses on minimizing crosstalk in high speed interconnects using measurement-based modeling.

Seminar Materials 2006-09-01

PDF PDF 1.50 MB
Testing Receiver Jitter Tolerance eSeminar FAQs 
Testing Receiver Jitter Tolerance eSeminar FAQs

Seminar Materials 2006-06-14

PDF PDF 50 KB
Jitter Measurements for High-Speed Digital 
Jitter Measurements for High-Speed Digital Transmission

Seminar Materials 2006-06-14

PDF PDF 44 KB
TDR vs. VNA Interconnect Characterization eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 18 KB

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