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Agilent EEsof EDA Newsletter - Product and Application News 
Keep tabs on the latest product and application news and review the archives of the Agilent EEsof EDA Newsletter.

内部通讯 2014-04-10

 
HDMI Cable Testing - BitifEye 
HDMI Cable Testing Solution from BitifEye and Agilent.

Solution Brief 2014-04-09

 
USB 3.0 Cable Testing - BitifEye 
USB 3.0 Cable Testing Solution from BitifEye and Agilent.

Solution Brief 2014-04-09

 
Oscilloscope Probe Switching - BitifEye 
Oscilloscope Probe Switching Solution from BitifEye and Agilent.

Solution Brief 2014-04-09

 
MIPI™ Phy S-Param & Impedance Conformance Test - Test Solution Overview Using the ENA Option TDR 

技术总览 2014-04-08

PDF PDF 2.92 MB
Discovering ADS 
A collection of Agilent EEsof EDA ADS video demonstrations and tutorials

基本演示 2014-03-20

 
优酷-EESof EDA 设计与仿真软件 
优酷-EESof EDA 设计与仿真软件

基本演示 2014-03-20

 
Agilent Method of Implementation (MOI) for MIPI M-PHY Conformance Tests 
Agilent Method of Implementation (MOI) for MIPI M-PHY Conformance Tests Using Agilent E5071C ENA Network Analyzer Option TDR

应用说明 2014-03-20

PDF PDF 978 KB
DOCSIS 3.1 Test Solution - Application Brief 
This “DOCSIS 3.1 Test Solution" app brief gives insight into Agilent solutions that can be used for testing DOCSIS 3.1 transmitters, receivers and components.

应用说明 2014-03-19

PDF PDF 1.30 MB
Digital Design & Interconnect Standards - Brochure 
Brochure shows Agilent’s high-speed digital solution set , a range of essential tools, measurement and simulation—that will help cut through the challenges of gigabit digital designs.

手册 2014-02-20

PDF PDF 6.47 MB
ADS 2014 Dramatically Improves Design Productivity and Efficiency 
Agilent announces a powerful new version of Advanced Design System software, ADS 2014. Designed to dramatically improve design productivity and efficiency with new technologies and capabilities, ADS 2014 is the software's most significant ADS release to date.

新闻资料 2014-02-20

 
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

文章 2014-02-18

PDF PDF 2.99 MB
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies 
This paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

文章 2014-02-18

PDF PDF 3.28 MB
Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI 
A technique of modeling and extraction of VCSEL devices for IBIS-AMI has been proposed.

文章 2014-02-18

PDF PDF 947 KB
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 
This paper presents a methodology to setup and analyze Simultaneous Switching Noise for DDR4 applications using Touchstone v2.0 models.

文章 2014-02-18

PDF PDF 8.07 MB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links 
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

文章 2014-02-18

PDF PDF 1.78 MB
Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver 
This paper shows the right combination of measurement and simulation techniques, and how the previously existing barriers for using de-embedding have been eliminated.

文章 2014-02-18

PDF PDF 3.82 MB
Mechanism of Jitter Amplification in Clock Channels 
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

文章 2014-02-18

PDF PDF 671 KB
Sanjay Gangal of EDACafé interviews Colin Warwick on New SI and EM Products at Designcon 2014 
Sanjay Gangal, V.P. Sales & Marketing at EDACafé interviews Colin Warwick, Product Manager at Agilent Technologies, at Designcon 2014, .

基本演示 2014-02-04

 
ADS Controlled Impedance Line Designer Solves Key Challenges in Designing Chip-to-Chip Links 
Agilent introduces Agilent EEsof EDA’s Controlled Impedance Line Designer. The software product quickly and accurately optimizes stack up and line geometry for multigigabit-per-second chip-to-chip links, using the most relevant metric.

新闻资料 2014-01-27

 
High Precision Time Domain Reflectometry - Application Note 
Time domain reflectometry (TDR) is a well-established technique for verifying the impedance and quality of signal pats in components, interconnects, and transmission lines.

应用说明 2014-01-23

Agilent Technologies to Exhibit Digital Design and Test Solutions at DesignCon 2014 
Agilent announced it will exhibit its high-speed digital solutions shown at DesignCon 2014, Jan. 29-30, Booth 201, in Santa Clara. The products offer a wide range of essential tools to help engineers design, simulate, analyze, debug and achieve compliant designs while meeting the challenges of gigabit digital designs.

新闻资料 2014-01-22

 
Quick Start for Signal Integrity Design Using Advanced Design System (ADS) 
This demo guide is a part of the high-speed digital design workflow for signal integrity engineers using Advanced Design System.

技术总览 2014-01-20

PDF PDF 3.80 MB
DDR4 Protocol Analysis - FuturePlus 
DDR4 Protocol Analysis from FuturePlus and Agilent.

Solution Brief 2014-01-08

 
J-BERT N4903B High-Performance Serial BERT - Data Sheet 
Updated J-BERT N4903B data sheet revision 1.3. Especially PCIe3 related enhancements covered by our PR in Jan 2013. Also covers all enhancements since SW releases 6.80 to 7.40

产品资料 2013-11-25

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