High-Speed Digital
- Design & Simulation: Download the Quick Start Guide
- Analysis & Debug: Download the Debugging application note
- Compliance: Visit the compliance web page
- Signal Integrity: Link to the PLTS technical overview
In digital standards, every generational change puts new risks in your path. We see it firsthand when creating our products and working with engineers like you. Agilent’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of. Agilent - achieve your best design.
Navigate the entire design cycle
Explore this web site for solutions within all four stages of the design cycle as well as the crucial—and integral—field of signal integrity analysis.
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By Application
- Signal Integrity (53)
- Design and Simulation of High-Speed Digital (28)
- High-Speed Digital Analysis (11)
- Debugging High-Speed Digital Signals (3)
- Compliance for High-Speed Bus and Serial Interconnects (7)
By Type of Content
- Seminar Materials (22)
- Training Materials (5)
- Classroom Training (1)
- Tradeshow (5)
- Seminar (8)
- Webcast - recorded (43)
- Webcast (2)
By Product Category
51-75 of 86
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Measurement based Modeling/Simulation for Gigabit Channels eSeminar FAQs
FAQs from the eSeminar Measurement-based Modeling and Simulation for Gigabit Channels
Seminar Materials 2006-05-11 |
PDF
56 KB
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Minimizing Crosstalk in Hi-Speed Interconnects using Measurement-based Modeling
This Presentation presented by Mike Resso (Agilent Technologies) focuses on minimizing crosstalk in high speed interconnects using measurement-based modeling.
Seminar Materials 2006-09-01 |
PDF
1.50 MB
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Modeling Optical Fiber Communication with Channel Simulation Webcast
Live broadcast March 6, 2013; 10am Pacific / 1pm Eastern
Webcast - recorded |
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New impedance measurement solutions & apps using 5 Hz to 3 GHz VNA
Originally broadcast April 19, 2011
Webcast - recorded |
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Optimizing PXI Modular Functional Test System Throughput Webcast
Originally broadcast April 27, 2011
Webcast - recorded |
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Oscilloscope Techniques for Precisely Measuring Small Signals Webcast
Original broadcast February 13, 2013
Webcast - recorded |
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Overcome High Speed Digital Design Challenges Webcast Series
Series of live and on-demand webcasts
Webcast - recorded |
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Overcome PI Challenges on Perforated Power/Groung Planes
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.
Seminar Materials 2012-01-19 |
PDF
2.30 MB
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Overcome Signal Integrity Challenges in the multigigabit(s) Era
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.
Seminar Materials 2011-12-15 |
PDF
781 KB
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Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages
A day in the life of a Memory Architect.
Seminar Materials 2011-10-24 |
PDF
1.86 MB
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PCI Express 3.0 Compliance - Successfully Navigating the Standard Webcast
Original broadcast May 7, 2013
Webcast - recorded |
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PCI Express 3.0 How to pass receiver compliance test for add-in cards and motherboards - webcast
Original broadcast October 27, 2011
Webcast - recorded |
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PCI Express(R) 3.0 Strategies for Transmitter and Receiver Validation
Originally broadcast Feb 10, 2011
Webcast - recorded |
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Physical Layer Test Challenges and Solutions for MIPI Interfaces Webcast
Original broadcast January 30, 2013
Webcast - recorded |
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Practical Guide to Making Advanced Jitter Measurements
Original broadcast September 19, 2012
Webcast - recorded |
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See the Future of High-Performance Real-Time Oscilloscopes
Original broadcast Apr 11, 2012
Webcast - recorded |
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Signal Integrity Design Using Channel Simulation and EM Co-design
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables
Seminar Materials 2010-04-21 |
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Signal Integrity eSeminar Series Q&A: Being Successful with Fully Buffered DIMM (FBD) Designs
The following Questions and Answers were created from the live eSeminar broadcast of January 25, 2005. You can view the archived eSeminar by going to
Seminar Materials 2005-01-25 |
PDF
60 KB
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Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.
Webcast - recorded |
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Solving Real World Jitter Problems for High-Speed Communications eSeminar FAQs
FAQs from the eSeminar
Seminar Materials 2006-05-11 |
PDF
53 KB
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Successful High Speed Digital Design with ADS, EMPro, and SystemVue
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.
Seminar Materials 2011-09-29 |
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Successful High Speed Digital Design with ADS, EMPro, and SystemVue: SI, PI, EMI
Various locations and dates
Seminar |
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SuperSpeed USB 3.0 Validation and Compliance Testing Challenges
Originally broadcast May 18, 2011;
Webcast - recorded |
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TDR vs. VNA Interconnect Characterization eSeminar FAQs
FAQs from the eSeminar
Seminar Materials 2006-05-11 |
PDF
18 KB
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Testing Receiver Jitter Tolerance eSeminar FAQs
Testing Receiver Jitter Tolerance eSeminar FAQs
Seminar Materials 2006-06-14 |
PDF
50 KB
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