High-Speed Digital
- Design & Simulation: Download the Quick Start Guide
- Analysis & Debug: Download the Debugging application note
- Compliance: Visit the compliance web page
- Signal Integrity: Link to the PLTS technical overview
In digital standards, every generational change puts new risks in your path. We see it firsthand when creating our products and working with engineers like you. Agilent’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of. Agilent - achieve your best design.
Navigate the entire design cycle
Explore this web site for solutions within all four stages of the design cycle as well as the crucial—and integral—field of signal integrity analysis.
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- Signal Integrity (21)
- Design and Simulation of High-Speed Digital (75)
- High-Speed Digital Analysis (42)
- Debugging High-Speed Digital Signals (16)
- Compliance for High-Speed Bus and Serial Interconnects (19)
Par type de contenu
- Spécifications (4)
- Notes d’application (102)
- Dépliants et révisions compétitives (19)
- Guide de sélection & de configuration (1)
- Brefs de solution (1)
- Démos (10)
- Articles et études de cas (9)
- Communiqués de presse (24)
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Agilent EEsof EDA Newsletter - Product and Application News
Keep tabs on the latest product and application news and review the archives of the Agilent EEsof EDA Newsletter.
Bulletin d'information 2013-05-14 |
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USB 2.0 Compliance Testing with Infiniium Oscilloscopes - Application Note
This Application Note discusses the Agilent solution for the USB 2.0 test suite. The Agilent solution is the only one-box solution that uses the official USB-IF scripts for precompliance ans compliance testing.
Notes d’application 2013-05-10 |
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2.02 MB
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Momentum Overview
Overview video of Agilent Momentum, the gold standard in 3D planar electromagnetic simulation that enables your design of optimum laminar structures.
Démonstration de base 2013-05-08 |
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ClioSoft Announces the Integration of SOS Design Data Management with Advanced Design System
ClioSoft's integrated solution offers ADS users seamlessly integrated revision control and enterprise design data management
Dossier de presse 2013-05-07 |
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Press Releases for N5990A
Press Releases for N5990A
Dossier de presse 2013-05-06 |
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High Speed Digital Design and Simulation Videos on YouTube
Agilent EEsof EDA's High Speed Digital Design and Simulation video playlist on YouTube.
Démonstration de base 2013-04-19 |
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EDA Support Services
Agilent Support Services for EDA Products offers customers several benefits otherwise not available. This service is designed to help you get the most out of your software purchases.
Brochure 2013-04-09 |
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128 KB
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Agilent Technologies Launches Recognition Program for EDA Experts
Agilent launches its Agilent Certified Expert recognition program for EDA experts. Eligible participants include individuals demonstrating a high level of expertise-both theoretical and practical-in applying Agilent EEsof EDA tools for product design and modeling.
Dossier de presse 2013-03-12 |
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Agilent Technologies Commits $90 Million Gift of Software to Georgia Institute of Technology
Agilent announces the largest in-kind software donation ever in its longstanding relationship with the Georgia Institute of Technology.
Dossier de presse 2013-02-04 |
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Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
Agilent and Signal Integrity Software, Inc. (SiSoft) announce guidelines that enable system designers to use advanced jitter and broadband analog capabilities when modeling high-speed serial devices.
Dossier de presse 2013-01-29 |
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DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.
Notes d’application 2013-01-24 |
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1.65 MB
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Agilent Technologies to Demonstrate Newest High-Speed Digital Design and Test Solutions at DesignCon
Agilent announces it will demonstrate its high-speed digital design and test solutions at DesignCon, Jan. 28- 31, at the Santa Clara Convention Center (Booth 201).
Dossier de presse 2013-01-15 |
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DDR Memory Design and Test – A Better Way
Agilent offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.
Brochure 2012-12-19 |
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5.17 MB
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DDR Memory Design and Test Overview
Brief overview of Agilent solutions for DDR design and test.
Brochure 2012-12-19 |
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1.14 MB
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Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links
Agilent introduces a redriver modeling solution designed to quickly and accurately solve the challenge posed by signal distortion in multigigabit-per-second systems.
Dossier de presse 2012-11-05 |
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High Speed Digital Design with Advanced Design System
This brochure describes 3 ADS suites of applicable simulators, libraries, and capabilities for signal integrity engineers.
Brochure 2012-11-02 |
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1.65 MB
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Frequency Domain Analysis of Jitter Amplification in Clock Channels
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained.
Notes d’application 2012-11-01 |
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257 KB
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ADS W2302EP/ET, W2500EP/ET, and W2312EP/ET Transient Convolution Products
Advanced Design System W2302EP/ET Transient Convolution Element, W2500EP/ETTransient Convolution GT Option, and W2312EP/ET Transient Convolution Distributed Computing 8-pack
Brochure 2012-10-30 |
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1.31 MB
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Agilent Technologies to Demonstrate High-Speed Digital Design Solutions at EPEPS
Agilent announces it will demonstrate its high-speed digital design solutions at EPEPS 2012, Oct. 22-23, at the Tempe Mission Palms Hotel, in Tempe, Ariz.
Dossier de presse 2012-10-22 |
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Explore the SERDES Design Space Using the IBIS AMI Channel Simulation Flow
Simulation of modern chip-to-chip links requires you abandon the SPICE-based approach and adopt a new approach based on an IBIS AMI channel simulation flow.
Notes d’application 2012-09-21 |
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467 KB
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STATS ChipPAC Launches QFN Package Design Kit for Agilent Technologies’ Advanced Design System
STATS ChipPAC announces the launch of its Quad Flat No-Lead (QFN) package design kit for ADS.
Dossier de presse 2012-09-12 |
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The Power of S-Parameters for High Speed Digital Design Tutorial
Learn to use S-parameters for high-speed digital designs with this video tutorial.
Matériel de promotion 2012-09-07 |
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S-parameter Series: Practical Application of the InfiniiSim Waveform Transformation Toolset Applicat
Presents and addresses five of the most common problems that confront engineers when trying to measure performance on high speed links, using an oscilloscope.
Notes d’application 2012-08-21 |
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These high-speed digital design and test resources are ready for you to explore
Receive the 2012 CD and view other videos of the Educational Forums & Workshops from DesignCon
Matériel de promotion 2012-08-15 |
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Agilent to Demonstrate Test Solutions at International Symposium on Electromagnetic Compatibility
Agilent will demonstrate its test solutions at the IEEE International Symposium on Electromagnetic Compatibility in Pittsburg, Aug. 5-10, 2012.
Dossier de presse 2012-07-18 |
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