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Phase-Locked Loops (PLL)

Design, synthesize, and simulate phase-locked loops (PLL) and frequency synthesizers with a comprehensive array of design and simulation tools. Make sure that critical performance goals can be achieved and reliably manufactured. Critical characteristics such as settling time and phase noise can be investigated and optimized for superior performance using Agilent's EDA software products such Advanced Design System (ADS), GoldenGate RFIC Simulator and/or Genesys.

After your design is complete, Agilent's test and measurement equipment, such as Signal Source Analyzer, Oscilloscopes and Spectrum Analyzers, can help you measure and verify your prototype and products.

The E5052B SSA Signal Source Analyzer provides fast and accurate measurements for PLL/VCO design and manufacturing, and contributes to producing high-quality profitable products with a shorter lead time. Phase noise, AM noise, Lockup time, VCO tuning performance, Harmonics, DC supply noise, you can evaluate all with this one box solution. 

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Presentation on ADS Simulation Power for 40-GBit Optical Wireline 
A detailed Presentation on ADS Simulation Power for 40-GBit Optical Wireline by Edmond Zauner, Agilent EEsof EDA, 12 June 2001.

Seminar Materials 2001-06-12

PDF PDF 2.10 MB
Presentation on Amplifier Design and Performance Testing 
This Presentation presents a design flow to create the circuit design for the Power Amplifier with the assistance of the two DesignGuides (Passive Circuit and Power Amplifier), which are new in ADS 1.3.

Seminar Materials 2000-11-01

PDF PDF 3.75 MB
Presentation on Amplifier Design in ADS for Radar Applications 
A Technical Presentation on amplifier design in ADS for radar applications was presented in Aerospace and Defense Symposium 2005.

Seminar Materials 2005-08-01

PDF PDF 5.61 MB
Presentation on High Efficiency RF Power Amplifiers using Bandpass DSM 
This Presentation by Shawn P. Stapleton presents the application of bandpass Delta-Sigma Modulators (DSM) to Switching Mode Power Amplifiers (SMPA) for cellular applications.

Seminar Materials 2001-06-12

PDF PDF 1010 KB
Presentation on High Yield MMIC Front-To-Back Design with ADS 2008 
This Presentation by J Sifri discusses how to take advantage of the latest productivity enhancements in ADS 2008 to implement a robust methodology for high yield MMIC designs.

Seminar Materials 2008-02-19

PDF PDF 4.28 MB
Presentation on Hybrid Time/Frequency Simulation Techniques 
A detailed Presentation (presented on 17 May 2002) describing Hybrid Time/Frequency Simulation Techniques.

Seminar Materials 2002-05-17

PDF PDF 2.93 MB
Presentation on Recent Advancements in RFIC Simulation Technology 
This Presentation details the needs of RF IC designers; faster-robust simulations, simulations of larger circuits, new simulation algorithms, behavioral model extraction for system-level verification.

Seminar Materials 2002-03-01

PDF PDF 1.34 MB
Presentation on Regenerative Payload Downconverter Simulation 
This Presentation describes Regenerative Payload Downconverter Simulation in detail.

Seminar Materials 2002-05-01

PDF PDF 1.04 MB
Presentation on RF Circuits Integration using CMOS SOI 0.25μm Technology 
This Presentation presents a brief overview of the Silicon On Insulator (SOI) technology and also introduces two RF designs performed successfully with 0.25μm SOI technology.

Seminar Materials 2002-03-01

PDF PDF 1.22 MB
Presentation on RF System-in-Package Design in ADS 
This Presentation by HeeSoo LEE (Agilent EEsof) presents an overview of RF System-in-Package (SiP) technology and also demonstrates ADS simulation capabilities for RF module applications.

Seminar Materials 2004-03-12

PDF PDF 5.65 MB
Presentation on Satellite Tuner Single Chip Simulation with ADS 
This Presentation describes STV0399 satellite tuner and use of ADS to simulate a whole front-end RF of a satellite receiver for digital TV.

Seminar Materials 2002-03-01

PDF PDF 2.65 MB
Presentation on Simulating Phase Locked Loops using ADS 
This Presentation details PLL simulation using ADS, Envelope simulation, PLL component behavioral modeling, Phase noise, Spurs, Fractional N-simulation and Divide ratio using sigma delta modulator.

Seminar Materials 2010-08-19

PDF PDF 1 MB
Presentation on Trends in Signal Integrity Tests 
A joint Presentation presented by Michael Reser and Rainer Plitschka (Agilent Technologies) on parametric tests for high-speed serial technologies focusing on latest trends in Signal Integrity tests.

Training Materials 2006-09-01

PDF PDF 2.13 MB
See the Future of High-Performance Real-Time Oscilloscopes 
Original broadcast Apr 11, 2012

Webcast - recorded

 
Speed of the Top-down design Methodology combined with the Silicon Accuracy 
A Joint presentation on Cadence and Agilent's RF/MS Design Solutions to help reduce risk, development time and costs, by providing accurate RFIC bottom-up verification.

Seminar Materials 2004-04-01

PDF PDF 1.58 MB
SSA presentation material – customer viewable slides with speaker notes 

Seminar Materials 2008-10-10

PDF PDF 1.01 MB
SuperSpeed USB 3.0 Validation and Compliance Testing Challenges 
Originally broadcast May 18, 2011;

Webcast - recorded

 
The Right Scope Probes Deliver Results 
Originally broadcast Feb. 22, 2011

Webcast - recorded

 
Understanding Jitter and Wander Measurements and Standards, Second Edition 

Training Materials 2003-02-01

PDF PDF 6.18 MB
USB 3.0 Physical Layer Test Challenges: Gen3 and Beyond Webcast 
Live broadcast June 13, 2013; 10am Pacific / 1pm Eastern

Webcast

 

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