数字和模拟设计
缩小范围
按应用
- 高速数字 (108)
- DDR 存储器 (3)
- HDMI (2)
- PCI Express® (5)
- 串行 ATA (SATA) (2)
- 串行连接 SCSI (SAS) (1)
- USB (2.0/3.0/无线) (4)
按内容类型
按产品类别
1-25 / 128
|
Introduction to EMI/EMC Challenges and Their Solution
Agilent EEsof EDA presentation on how to, "Overcome High Speed Digital Design Challenges".
研讨会演示 2012-02-16 |
|
|
观看网络研讨会录像--为下一代 HDMI 标准做好准备
为下一代 HDMI 标准做好准备
培训资料 2012-02-12 |
|
|
Overcome PI Challenges on Perforated Power/Groung Planes
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.
研讨会演示 2012-01-19 |
|
|
Overcome Signal Integrity Challenges in the multigigabit(s) Era
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.
研讨会演示 2011-12-15 |
|
|
Design and Test Challenges in Next Generation High-Speed Serial Standards
Attend this FREE education workshop at DesignCon 2012, brought to you by Agilent Technologies, Official Host Sponsor of the conference.
培训资料 2011-11-29 |
|
|
View the recorded webcast - How to handle USB 3.0 physical layer test requirements
How to handle USB 3.0 physical layer test requirements.
培训资料 2011-11-08 |
|
|
View the recorded webcast - Be ready for the next generation HDMI standard
Be ready for the next generation HDMI standard
培训资料 2011-11-08 |
|
|
Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages
A day in the life of a Memory Architect.
研讨会演示 2011-10-24 |
|
|
Successful High Speed Digital Design with ADS, EMPro, and SystemVue
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.
研讨会演示 2011-09-29 |
|
|
Signal Integrity Design Using Channel Simulation and EM Co-design
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables
研讨会演示 2010-04-21 |
|
|
USB 3.0 Superspeed PHY Testing Challenges: Verify your 5Gbps design to the specification
培训资料 2009-04-15 |
|
|
Tips to Debugging DDR 1, 2 and 3 Physical and Protocol Layer Issues webcast
培训资料 2009-01-06 |
|
|
ADMF: Facing the challenges of Super speed USB 3.0 Product Development
Agilent Digital Measurement Forum (ADMF): Facing the challenges of Super speed USB Product Development
研讨会演示 2008-11-12 |
|
|
Hacking the Backplane:Complete Differential Channel Characterization & Analysis from 4-port Meas.
研讨会演示 2008-11-09 |
|
|
How to Solve DDR Signal Integrity Validation Challenges
How to Solve DDR Signal Integrity Validation Challenges
培训资料 2008-02-13 |
|
|
Why Do Measurement-based Channel Modeling?
Adobe .pdf of the paper presented at the High-Speed Digital Seminar, Ensuring MultiGigabit Design Success
研讨会演示 2008-01-20 |
|
|
Minimizing Crosstalk in Hi-Speed Interconnects using Measurement-based Modeling
This Presentation presented by Mike Resso (Agilent Technologies) focuses on minimizing crosstalk in high speed interconnects using measurement-based modeling.
研讨会演示 2006-09-01 |
|
|
Jitter Measurements for High-Speed Digital
Jitter Measurements for High-Speed Digital
Transmission
研讨会演示 2006-06-14 |
|
|
Testing Receiver Jitter Tolerance eSeminar FAQs
Testing Receiver Jitter Tolerance eSeminar FAQs
研讨会演示 2006-06-14 |
|
|
Solving Real World Jitter Problems for High-Speed Communications eSeminar FAQs
FAQs from the eSeminar
研讨会演示 2006-05-11 |
|
|
Characterization and Modeling of a High Speed Backplane Differential Channels eSeminar FAQs
FAQs from the eSeminar
研讨会演示 2006-05-11 |
|
|
Jitter Analysis: What Works, What Doesn't & Why eSeminar FAQs
FAQs from the eSeminar
研讨会演示 2006-05-11 |
|
|
Jitter in Digital Circuits eSeminar FAQs
FAQs from the eSeminar
研讨会演示 2006-05-11 |
|
|
Analyzing Digital Jitter and its Component eSeminar FAQs
FAQs from the eSeminar
研讨会演示 2006-05-11 |
|
|
Jitter Measurements with a High-Speed Scope eSeminar FAQs
FAQs from the eSeminar
研讨会演示 2006-05-11 |
|
