High Speed Digital Design Seminar

High Speed Digital Design Seminar

MultiGigabit Serial Design – Ensuring Design Success
The demand for more system bandwidth has driven the design of several new protocol-rich high-speed serial interconnect standards. Today’s challenge is incorporating 2.5 to 5.0 Gb/s data rates in designs like PCI Express, SATA, FBD, and DisplayPort, with 6 to 10 Gb/s variation coming. This presentation will discuss the important factors in characterizing the physical layer of differential serial interconnects such as minimizing reflections with quality impedance design, minimizing jitter effects, utilizing new compliance tools, and more.

Successfully Negotiating The PCI Express 2.0 Super Highway Towards Full Compliance
PCI Express 2.0 operates at twice the data rate (5.0 Gb/s) compared to PCI Express 1.x technology. Significant changes in physical layer electrical measurements, and link and transaction layer compliance tests were implemented. This presentation review these changes, how to validate your motherboard and add-in card device under the 2.0 spec helping to ensure that you will be ready to qualify for the Integrator’s List. In addition, you’ll learn about how to ensure your designs are taking maximum advantage of the upgraded throughput offered by PCI Express 2.0.

Validating of DDRII/III Memory Designs
With increasing data rate and tighter requirement for DDRII/III DRAM designs, the test and validation tasks have been made more difficult for engineers. Not only does the DRAM need to meet the electrical specifications, but also the protocol requirements. On top of that, the probing solutions today might be inadequate to meet the bandwidth, signal integrity performance, form factor and convenience for making accurate and repeatable measurement. This presentation explains how your logic analyzer and oscilloscope can be used to validate your DDRII/III designs, including new BGA probing solutions and measurement automations tools.

You’ve Measured The Jitter, Now How Do You Reduce It?
While making accurate measurements is important, it is just one part of the overall jitter problem. This presentation will review both time domain and frequency domain analysis techniques, including phase noise analysis. This allows us go beyond the measured jitter and identify the root causes of jitter problems. Topics such as the relationship between reference clocks and data transmitters and how jitter propagates in a communications system will be investigated.

HDMI - TBD

Why Do Measurement-based Channel Modeling?
This presentation will discuss various measurement and modeling techniques that are used to characterize today’s high speed digital channels. Basics of VNA calibration techniques, S-parameter de-embedding, mixed mode S-parameters, TDR, eye diagram, and jitter will be covered utilizing the ADS (Advanced Design System) and PLTS (Physical Layer Test System) as signal integrity analysis tools. Key learnings will include knowing which of the performance figures-of-merit are most important, how to assure good correlation between measurements and modeling, identifying basic channel topology in multiple domains, and optimizing your design for high speed.