DesignCon 2008 Technical Paper Presentations
The following papers will help address some of the signal integrity challenges associated with designing, testing, and validating high-speed digital interconnects used in physical layer test systems.
DesignCon 2008 Best Paper award in the Test and Measurement category
“Performance at the DUT” is the ideal specification for an ATE test fixture. Fast slew rates of multi-gigabit signals can easily be degraded by the interaction of the test fixture's PCB, socket, and DUT interfaces, making it difficult to predict the performance at the DUT. This paper presents the results of an effort to address these challenges and show results for an application running at 6.4 Gbps on an ATE system. Topics include probing techniques for characterizing the test fixture at the DUT socket interface, calibration and 3D-EM simulation methods for de-embedding the probe effects, and synthesized performance at the DUT. The significant contribution of multiple companies collaborating to address this “Performance at the DUT” measurement challenge emphasizes the variety of technologies that are coming together to solve high speed SERDES applications and the honor of winning Best Paper in the Test and Measurement Category of DesignCon 2008 shows the importance of this topic in the industry.
Printed circuit board (PCB) materials directly influence attenuation and NEXT/FEXT crosstalk signal integrity of an Automated Test Equipment (ATE) test fixture design. Balancing performance, cost, and ease of fabrication requires a quantitative understanding of the impact that the dielectric material has on the performance of a multi-gigabit test fixture signal path. An understanding of how the material will perform when used to fabricate 20+ layer count ATE boards with thicknesses over 200 mils is required. This paper provides an analysis of various test fixture PCB materials for a nominal test fixture test fixture design with 25 cm (10 inches) of path length and data rates up to 43 Gbps.
12-port differential S-parameters contain the complete behavior of up to three independent channels in a high-speed serial interconnect. This new application note discusses how this information can be used to interpret the interconnect performance of these types of measurements.
As serial bit rates continually increase, backplanes must be designed and built to last through many line card product generations. Although the backplane may not contain any active components, a significant effort must be made to characterize and verify its performance. This new application note discusses some design tools for characterizing high-speed interconnects used in multi-gigabit serial backplanes.
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