What is an Instruction Register?
The Instruction Register lets you define the test to be performed, or the test data register to be accessed, or both during boundary scan test. Each Instruction Register cell comprises a shift-register flip-flop and a parallel output latch. The shift registers hold the instruction bits moving through the Instruction Register. The latches hold the current instruction.
Many mandatory and optional instructions are defined by IEEE Standard 1149.1. Design-specific instructions can also be added to a device. The minimum size of the Instruction Register is two cells. The size of the register dictates the size of the instruction codes that can be used: code size must match the length of the register.
The two least significant register cells must load a fixed binary "01" pattern during a controller state called CAPTURE-IR. The instruction shifted into the register is latched onto the outputs at the completion of the shifting process; this must occur during the UPDATE-IR state only. This requirement ensures that the instruction changes only at the end of the Instruction Register (IR) scanning sequence. The values latched onto the Instruction Register outputs define the test to be applied, the test data register to be accessed, or both.
When a reset is applied by the TAP Controller, or after the controller enters the TEST-LOGIC-RESET state, the IDCODE instruction must be latched onto the Instruction Register outputs. If the device does not have an ID (identification) Register, then the BYPASS instruction must be loaded onto the outputs. Table 1 shows the behavior of the Instruction Register during each TAP Controller.
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