What types of boundary scan tests can be applied on the Agilent Medalist i3070 in-circuit tester (ICT) platform?
Boundary scan can be applied to perform several different types of test on the Agilent Medalist i3070 in-circuit test series, with each type of boundary scan test serving different purposes to meet the wide range of electronic manufacturing test needs. The different test types are:
- Powered shorts
- TAP integrity
- Connect tests
- Dot6 test
- Silicon nail
|Boundary scan tests on Agilent Medalist i3070 ICT||Functions|
|Powered Shorts Test||Tests for solder shorts on the connections between boundary-scan nodes that do not have physical access and conventional nodes of any other type that do have physical access.|
Powered shorts test fixes the direction that bidirectional cells are tested: those cells selected as drivers by the software are tested only as drivers; those not selected are tested only as receivers.
One powered shorts test is generated for each Boundary scan chain on the board.
NOTE: The exceptions are power and ground nodes, disable nodes, and TAP nodes. Shorts to power or ground are detected by interconnect test. Most shorts to TAP nodes are detected by integrity test.
|TAP Integrity Test||Verifies that the Test Access Port (TAP) of all the boundary-scan devices in the chain operate properly. If this test fails, testing stops, and power is removed from the board. This test is a preamble to all other boundary-scan tests: it is an integral part of each test and is executed before each test runs.|
|Interconnect Test||Tests the connections from one boundary-scan device to the other boundary scan devices in the chain. One interconnect test is generated for each boundary scan chain on the board. This test checks primarily for shorts, but most opens will also be detected. If this test fails, testing stops, and power is removed from the board. Interconnect test attempts to use only one driver in the case of bussed nodes. This helps keep tests shorter, helps diagnostics, prevents bus fights, and minimizes the potential for device damage.|
Interconnect test fixes the direction that bidirectional cells are tested: those cells selected by the software as drivers are tested only as drivers; those not selected are tested only as receivers. Interconnect tests require the use of only four testhead resources; three drivers (TMS, TCK, TDI) and one receiver (TDO).
NOTE: If device disabling or conditioning is necessary for other devices on the board, additional drivers might be required.
|Buswire Test||Created when bussed drivers are present in the chain. Under certain circumstances, interconnect test must be executed with multiple device outputs driving test patterns onto the same (bussed) node. If one of the drivers was disconnected from the node, it would go undetected. Interconnect test could also be executed with two or more drivers connected to one node, but with only one driver enabled. For these reasons, buswire test turns drivers on one at a time to check for opens, and tests the operation of all drivers. One buswire test is generated for each chain on the board. Buswire test verifies the operation of bidirectional pins by generating separate vectors to check their operation as drivers, then as receivers.|
|Connect Test||Tests for opens on each device, one at a time (u1, . . . uy), until the entire chain has been tested. This test checks for opens on only the inputs and outputs of devices that have physical probes assigned. One connect test is generated for each boundary-scan device in the chain that has one or more I/O pins accessible from the testhead. |
For larger devices that exceed the available number of testhead resources—for example, testing a 300-pin ASIC when only 200 resources are available—you can (manually) split the connect test into two or more smaller tests.
Connect test verifies the operation of bidirectional pins by generating separate vectors to check their operation as drivers, then as receivers.
|Dot 6||Tests for the interconnection of high-speed AC-coupled differential signals between devices in accordance to the IEEE 1149.6 standard. |
Recent proliferated use of ac-coupled signals with its series coupling capacitors render the signals at the boundary scan receiver undetectable using the conventional IEEE 1149.1 means as digital signals traversing a capacitor will be transform into a decaying signal.
Test file-names in the i3070 are suffixed with the word “aio”.
|Silicon Nails||Tests traditional logic (non-boundary scan devices) even if they do not have physical probes assigned to its pins. If these devices are connected to boundary scan devices then the boundary scan cells within these boundary scan devices can be used as drivers and receivers much like a physical probes.|
|Cover Extend Technology (CET)||This is a hybrid test between boundary scan and VTEP test. |
VTEP test is an Agilent vectorless test that employs the capacitive sensing of stimulus signal traversing a pin. An open defect will disallow the traversing of signal and therefore a low VTEP reading would indicate this defect.
Traditional VTEP test require physical probes to be assigned. CET do not need physical probes and instead rely on the boundary scan cells to drive the stimulus signals.
CET helps extend test coverage further to non-silicon components like connectors and sockets. CET on devices is possible too.
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