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High Speed Digital Design Flow

Signal Integrity, Power Integrity, EMI, and EMC

Solve High Speed Digital Design Challenges with ADS and Other Agilent Tools

When digital signals reach multigigabit speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job. Agilent’s high speed digital solution includes EDA design and simulation tools that will help you cut through the challenges of multigigabit digital designs. Our tools provide views into the time and frequency domains, revealing the underlying problems and ensuring compliant designs. With Agilent, you’ll be equipped to pinpoint, optimize and deliver - on time.

With ADS and other tools from Agilent you can:

  • Analyze complete chip-to-chip links by co-simulating individual components, each at its most appropriate level of abstraction: channel-, circuit- or physical-level
  • Import frequency-domain s-parameter models accurately into time-domain circuit and channel simulations, using our patented causality and passivity algorithms
  • Determine ultra-low BER contours in seconds not days using the statistical and bit-by-bit modes of Channel Simulator
  • Import transceiver models in IBIS format (both traditional and AMI) and in netlist format (both unencrypted and encrypted with the Agilent key)
  • Import post-layout artwork from enterprise PCB tools from Cadence, Mentor, Zuken, etc. for EM analysis of power integrity and signal integrity issues
  • Generate IBIS AMI models in days not months

Recommended High Speed Digital Design Flow

Agilent’s goal is to provide the industry’s premier HSD EDA software. We offer an integrated design flow with best-in-class, measurement-hardened technologies, tuned to the needs of the high speed digital engineer.

The diagram below illustrates the workflow.

Recommended High Speed Digital Design Flow

  1. First collect IC models of the SerDes or parallel bus I/O. For example, on FPGAs, the I/O are typically called multi-gigabit-tranceivers (MGTs) and the FPGA vendor will provide an IBIS AMI, traditional IBIS, or SPICE-like netlist model. The package model might be included inside the IBIS model or supplied separately as an s-parameter model, for example. Step 1 is usually completed for you by your IC vendor. You just need to obtain the models. IC vendors often use our SystemVue product to generate their models quickly and easily, but any industry-standard models, however generated, will work.
  2. Combine the IBIS AMI IC models (shown in cyan) with a placeholder for the channel (shown in gray) using ADS Channel Simulator. In ADS, the pre-layout channel is typically modeled using the Controlled Impedance Line Designer. It lets you optimize stack up and line geometry using metrics that matter, such as eye opening. This is in contrast to other tools that limit you to only traditional metrics like frequency roll off. You can model only the through channel (as shown) but typically you’ll also add aggressor channels (not illustrated here) to model the effect of crosstalk onto the victim channel. The goal is to generate layout constraints for the constraint manager of your physical designer’s third-party enterprise PCB tool (e.g. Allegro from Cadence, Expedition from Mentor, or CR-5000 from Zuken). You’ll answer questions like “What is the best stackup?” “What should the geometry of my controlled impedance lines be?” “How closely can the signal lines be placed before crosstalk occurs?” “Do I need to backdrill my vias in order to reduce reflections from the stubs”
    If IBIS AMI SerDes models are not available to you, you can instead set the parameters of the built-in generic models using information (e.g. number of pre-emphasis or EQ taps) from the vendor’s data sheet.
  3. If you have IC models in the traditional IBIS models or SPICE-like netlist format, you can run them in ADS Transient and perform the same exercise as in step 2. Briefly, the tradeoff between ADS Channel Simulator and ADS Transient is that Channel Simulator is typically 1000x faster than Transient for SerDes topologies with embedded clocking, but Transient offers greater flexibility in terms of topology, clocking, and simultaneous switching noise (SSN). For example, parallel busses with source synchronous clocking can be modeled in Transient but not Channel Simulator. Transient can also handle power integrity effects like SSN. In many case, the choice between simulators will be dictated by the style of IC model available to you.
  4. Your physical designer will take the fruits of the pre-layout stages to set the constraints of their enterprise PCB tool’s autorouter. For more details, refer to the ADS Example Workspace: “Generating Parameters For Third-party, Constraint-based PCB Layout Tools Using Pre-Layout Simulations” (Knowledge Center login required).
  5. The autorouter will take the pin-to-pin connectivity table and the layout constraints and create a candidate layout.
  6. Import the candidate layout into ADS and prepare for application of the EM fields solvers in ADS and EMPro. You may select critical nets for analysis, cookie cut around them, set up ports and substrate material properties and so on. Method of moments is typically the most efficient way of creating the EM model, but in some cases our FEM or FDTD solvers might be more efficient.
  7. Swap out the placeholder pre-layout channel (the gray box in step 2) with the EM model (illustrated as the purple box in step 7). You can reuse the rest of the Channel Simulation or Transient Simulation schematic. You can associate a “look alike” symbol with an EM model and use it in a schematic with a time- or frequency-domain simulation controller. When the channel metrics (e.g. BER contours) of the candidate meets your specifications, then you’re ready to go to manufacturing.
  8. Once you receive the prototype back from fabrication, you can measure it before and after component attachment with a VNA and oscilloscope. You can correlate simulated and measured metrics to close the loop between your model library and the end-to-end performance.

With this flow, you’ll save boards spins, time, and money versus the non-deterministic “cut and try” approach.

Further Reading

Return to Design and Simulation of High Speed Digital.