What do the TAP, JTAG pins/port and 1149.1 pins/port have in common?
From a technological perspective, they actually refer to the same thing. According to the IEEE 1149.1 standard, the official standard name is Test Access Port (TAP). The TAP is a general-purpose port that connects the boundary scan control signals to the device boundary scan cells and functions.
The TAP signals include the following:
- TDI (Test Data Input) - Provides serial inputs for test instructions shifted into the Instruction Register and for data shifted through the Boundary Register or other data registers. Values are clocked into the selected register on a rising edge of TCK.
- TDO (Test Data Output) - TDO is the serial output for test instructions and data from the Boundary Register or other data registers. The contents of the selected register (instruction or data) are shifted out on the falling edge of TCK.
- TCK (Test Clock) - The Test Clock input provides the clock for the test logic. TCK is a dedicated input that allows the serial test data path to be used independent of component-specific system clocks. It also permits shifting of test data concurrently with normal component operation.
TMS (Test Mode Select) - This optional input provides asynchronous initialization of the TAP Controller, which in turn causes asynchronous initialization of other test logic included in the design. The reset places the device in the normal operating mode and makes the Boundary Register inactive.
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