Agilent's Education Forum at DesignCon 2011
Date: Monday, January 31, 2011
Time: 1:30pm-4:30 pm
Title: USB 3.0 Serial Link Design, Optimization and Validation
Thanks to the Internet and the communications revolution, an enormous amount of content is being generated, processed and consumed at a staggering rate. In parallel, mass storage technologies are seeing significant innovation. Storage is becoming inexpensive and densities are increasing, driving content sharing. Such factors have made the need for a next-generation interconnect technology all the more critical. The USB 3.0 specification offers an elegant and seamless solution to this need. With the growing interest in USB 3.0 has come increased focus on proper USB 3.0 serial link development. This tutorial will focus on three key areas that are essential to ensuring the success of a USB 3.0 product, including:
Modeling and Simulation - Accurate modeling and simulation plays a key role in first-pass design success of USB 3.0 products. This portion of the tutorial will focus on USB 3.0 serial link end-to-end physical layer modeling and simulation. It will cover measurement and extraction of the physical layout for its SI, PI and EMI performance using various electromagnetic simulators, measurements and de-embedding techniques. To determine link reliability, the extracted interconnect component will be integrated with various SERDES models (e.g., behavioral, transistor level and IBIS AMI). A step-by-step procedure for creating IBIS AMI models from SERDES representation using algorithmic models, and simulated and measured data will also be presented. A real-world USB 3.0 DUT will be used to aide in this discussion and illustrate how to determine optimum link performance.
Interconnect Analysis Traditionally - high-speed cable test is performed in a signal integrity lab and requires multiple measurements from various pieces of test equipment to assure compliance and interoperability. Using a more modern approach, just one test system can provide all necessary measurements (e.g., differential insertion loss, differential impedance, near-end crosstalk, intra-pair skew and eye diagram analysis). Each measurement can be programmed into a single “test suite” to provide a one-button compliance test. Specialized software packages can be used to control the test system, greatly reducing test time and enabling generation of custom test reports. This portion of the tutorial will focus on how the test engineer can use this “new age” test technology to enhance ease-of-use for USB 3.0 cable testing. A USB 3.0 test fixture and Physical Layer Test System provides the design case study for this discussion. De-embedding and other advanced calibration techniques will also be discussed.
Compliance and Validation Testing - Compliance and validation testing of serial links has evolved as data transfer rates have steadily climbed upward. So too has the approach to transmitter characterization. At 5 Gbps over 3 meters of cable + interconnect traces, the electrical margins are a fraction of what they were for USB 2.0 speeds. This has forced a significant change in the measurement methodology for both the transmitter and receiver. This portion of the tutorial will demonstrate transmitter compliance testing with embedded channel models. In particular, it will show how USB 3.0 compliance testing incorporates S-parameters.
Date: Wednesday, February 2nd, 2011
Time: 8:30 am to 12:00 pm
Title: A Simple, Yet Powerful Method to Characterize Differential Interconnects
Up to now, it has been a challenge to routinely and directly measure an S-parameter behavioral model of a structure that does not contain the artifacts of the fixtures, connectors, probes and launch. In addition, to obtain the s-parameters of the test fixture that needs to be removed has previously required such drastic steps as destructive connector removal for probe access. The new and simple approach that will be illustrated, explained and demonstrated in this tutorial, will introduce a new calibration technique based on the 2x thru fixture removal process. This new technique will be applied to four very different structures: circuit board transmission lines to routinely measure their differential impedance and loss, cable assemblies, board to board connector systems and cable to board connector systems. The interconnect design flow will be highlighted so that it is clear what other tools can utilize the input and output fixture Touchstone files for standard de-embedding techniques in downstream processes.