嵌入式 PCI Express® 应用的调试和表征
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PCI Express® is the wave of the future for high performance I/O in both desktop and industrial/embedded applications. It offers the benefits of reduced power consumption, scalability of bandwidth, increased data throughput and improved signal integrity. It replaced legacy bus-based PCI and PCI-X technologies, and is now migrating from the desktop to embedded applications. This presents new challenges for the embedded designer on multiple fronts. The transition from parallel to serial technology requires very different debug methods and tools. Second, many of these designs will leverage silicon and other IP already on the market. A key concern is how to evaluate, choose and select components and IP for your specific application. Lastly, probing an embedded link is significantly more challenging compared to motherboards and add-in cards since it is unlikely a standard PCI Express connector exists between transmitter and receiver. This presentation provides an overview of the latest developments in PCI Express standards and hints on how to choose off-the-shelf IP, ASSPs, or other PCI Express compatible components. We will provide examples of proven probing techniques that support both physical layer measurements as well as link level debug of PCI Express transactions.
Who should view this Webcast
R&D designers, engineers, and project managers working on high-speed digital designs; who spend a significant amount of time in the debug and validation phase dealing with signal integrity related problems in their designs.
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PCI EXPRESS is a registered trademark of the PCI -SIG
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