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Boundary Scan Test Methods for DDR Memories

Webcast - grabado | Where & When

In-circuit testing of DDR Memories has become increasingly difficult. This Webcast will discuss methods of DDR test development and debug. It will describe the challenges facing engineers writing these tests and offer some solutions. The Webcast will focus on Boundary Scan testing of DDR memories.

Who should attend: ICT Test Developers

Where & When

Price Date(s) Location For more information
Free 2010-10-25 09:00
Local
At Your PC View the recording of the May 18, 2010 WebEx presentation 

Prices shown are list prices and are subject to change without notice.