Overcome High Speed Digital Design Challenges Webcast Series
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job. You’ll need techniques taken from communication science (like adaptive equalization) and tools taken from microwave engineering (like field solvers) to overcome the three main design challenges: signal integrity, power integrity, and EMI/EMC. In this series of webcasts we’ll show you how to improve time-to-market by proactive application of these modern techniques.
Part 1 - Is Simulation a Requirement for Memory Designs?
February 20, 2013; 10:00 am Pacific / 1:00 pm Eastern
The Double-Data-Rate DDR memory channel is found in a wide range of applications: smartphones, tablets, notebooks, desktops, and servers.
The famous DDR3 can reach 2.133GBps per cupper lane at 1.5V SSTL15 technology, while DDR4 starting at 2.4GBps per lane with 1.2V POD12 technology trying to hit 3.2GBps. How can the designer find out the key enablers to make the DDR3 and DDR4 channel work successfully? Can we depend on trial and error to meet the target?
In this webcast, we are proposing simulations hardened by measurements to detect the key enablers of the DDR3 and DDR4 memory channel. We will show an example of DDR3 memory channel running at 2.133GBps and how DDR4 technology can help us reach 2.4GBps.
Part 2 - Modeling Optical Fiber Communication with Channel Simulation
March 6, 2013; 10:00am Pacific / 1:00pm Eastern
In the multigigabit per second regime, rack-to-rack copper cables distort picosecond rising and falling edges after only a few meters of propagation. To achieve a building and campus run lengths of 300 meters at these data rates, it is necessary to use optical fiber communication modules. We have developed a pre-standard extension to the IBIS AMI flow that enables component vendors to build models of their opto links, for use by their customers who are designing the models into systems. The models run in ADS Channel Simulator. This flow enables end-to-end optimization and eliminates costly, time consuming, and non-deterministic rework. This approach can also be used to model mid-channel electrical repeaters such a redrivers and retimers.
Part 3 - What on Earth is Jitter Amplification, and Why Should I Care?
April 9, 2013; 10:00am Pacific / 1:00pm Eastern
High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a lossy channel even when the channel is linear, passive, and noiseless. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.
WHO SHOULD ATTEND
Signal integrity engineers and high speed digital engineers of multigigabit links who are running into effects previously only seen in RF and microwave circuits.
Overcome Signal Integrity Challenges in the Multigigabit/s Era
Original broadcast date December 15, 2012
To mitigate channel impairments in the multigigabit/s regime, modern SERDES employ signal processing techniques such as receive equalization. The equalizer taps and other parameters can be tuned to the optimum values in the field via register settings available to the user. However, to find these optimum values, it is necessary to explore the design space. The design space multiplies combinatorially when one considers transmitter parameters and channel design parameters. In addition, the logic block that implements the signal processing function can be quite large -- tens of thousands of transistors -- making conventional SPICE-like transient simulations with netlist-based IC models impractical. New simulation techniques are needed as well as new types of IC models. In this webcast we'll explain how channel simulation and IC models based on the emerging IBIS 5.0 AMI flow can solve these challenges.
Overcome PI Challenges on Perforated Power/Ground Planes
Original broacast date January 19, 2012
Traditional power integrity tools fail when applied to PCBs and packages with heavily perforated power/ground planes because they were built for high layer count boards that can afford the luxury of solid power/ground planes. Thus, they sacrifice generality to gain speed and capacity. In this webcast, we'll explain a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.
Introduction to EMI/EMC Challenges and Their Solution
Original broadcast date February, 16 2012
In the multigigabit era, passing EMI/EMC specs is increasingly challenging. Discovery of an EMI/EMC failure late in the project can force a recourse to makeshift solutions that add unit cost and delay time to market.
In this webcast, we explain the causes of EMI/EMC and propose a proactive methodology that we dub “Virtual EMI lab.” This methods uses EM simulation to identify and mitigate issues early in the design when many more design options are available. The “Virtual EMI lab” discipline includes both pre-manufacture EM simulations and methodology refinement via post-manufacture co-relation against measured data from EM chambers and EM scans. Our examples include: trace emission from MA/CMD memory, return-current emission on data nets on packages, SSO emission due to Icc(t), and HDMI cable emission due to grounding issues between the connector and the PCB.
Training & Event Materials
Overcome Signal Integrity Challenges in the multigigabit(s) Era
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.
Seminar Materials 2011-12-15
PDF 781 KB
Overcome PI Challenges on Perforated Power/Groung Planes
This presentation explains a different approach that's applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.
Seminar Materials 2012-01-19
PDF 2.30 MB